?? lcd_graph.vhd
字號:
-------------------------------------------- test wy渨ietlacza graficznego LCD
--
-- Program rysuje na wy渨ietlaczu graficznym G121600N000 (Seiko) regularny
-- wz髍 szachownicy.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LCDgraph is
port (
clk: in std_logic; -- clock
E_LCD: out std_logic; -- LCD Enable
DI_LCD: out std_logic; -- Data/Instruction
CS1_LCD: out std_logic; -- Chip Select 1
CS2_LCD: out std_logic; -- Chip Select 2
RST_LCD: out std_logic ; -- LCD Reset
D_LCD: out std_logic_vector(7 downto 0) -- licznik
);
end LCDgraph ;
architecture LCD_architecture of LCDgraph is -------------------------------
type state_type is (s0,s1,s2,s3);
attribute enum_encoding: string;
attribute enum_encoding of state_type: type is "00 01 10 11";
signal cs: state_type :=s0;
signal ns: state_type;
signal cnt: std_logic_vector(9 downto 0) := (others =>'0');
begin
u1: process(clk) -- proces zmiany stan體 w maszynie stan體
begin
if(clk'event and clk='1') then
cs <= ns;
cnt <= cnt+1; -- licznik zliczaj筩y zbocza zegara
end if;
end process;
u2: process(cs) -- realizacja maszyny stan體
begin
case cs is
when s0=>
ns<=s1;
RST_LCD <= '0'; -- reset wy渨ietlacza
when s1=>
ns<=s2;
RST_LCD <= '1';
DI_LCD <= '0';
D_LCD <= x"3f"; -- LCD on (w徹cz wy渨ietlacz)
when s2=>
ns<=s3;
RST_LCD <= '1';
DI_LCD <= '1';
if cnt(3) = '1'then
D_LCD <= x"0f"; -- wz髍 kratki co 8-bit體 licznika
else
D_LCD <= x"f0";
end if;
when s3=>
ns<=s2;
RST_LCD <= '1';
DI_LCD <= '0';
D_LCD<= "10111" & cnt(9 downto 7); -- zmiana wiersza co 64 stany
when others =>
ns<=s0;
RST_LCD <= '1';
DI_LCD <= '0';
D_LCD<= x"00";
end case;
end process;
E_LCD <= clk;
CS1_LCD <= '0';
CS2_LCD <= '0';
end LCD_architecture ;
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