/********************************************************************************    File Name:  me.v*      Version:  1.0*         Date:  January 22, 2000*        Model:  Manchester Encoder Chip**      Company:  Xilinx***   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY *                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY *                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.**                Copyright (c) 2000 Xilinx, Inc.*                All rights reserved*******************************************************************************/module me (rst,clk16x,wrn,din,tbre,mdo) ;input rst ;input clk16x ;input wrn ;input [7:0] din ;output tbre ;output mdo ;wire clk1x ;reg clk1x_enable ;wire clk1x_disable ;reg [3:0] clkdiv ;reg [3:0] no_bits_sent ;wire mdo ;reg tbre ;reg [7:0] tsr ;reg [7:0] tbr ;reg parity ;reg wrn1 ;reg wrn2 ;// Form 2 FF register for write pulse detectionalways @(posedge rst or posedge clk16x)if (rst)beginwrn2 <= 1'b1 ;wrn1 <= 1'b1 ;endelsebeginwrn2 <= wrn1 ;wrn1 <= wrn ;end// Enable clock when detect edge on write pulsealways @(posedge rst or posedge clk16x)beginif (rst)clk1x_enable <= 1'b0 ;else if (wrn1 == 1'b1 && wrn2 == 1'b0)clk1x_enable <= 1'b1 ;else if (no_bits_sent == 4'b1111)clk1x_enable <= 1'b0 ;end// Generate Transmit Buffer Register Empty signalalways @(posedge rst or posedge clk16x)beginif (rst)tbre <= 1'b1 ;else if (wrn1 == 1'b1 && wrn2 == 1'b0)tbre <= 1'b0 ;else if (no_bits_sent == 4'b1010) tbre <= 1'b1 ;elsetbre <= 1'b0 ;end// Detect edge on write pulse to load transmit bufferalways @(posedge rst or posedge clk16x)beginif (rst)tbr <= 8'h0 ;else if (wrn1 == 1'b1 && wrn2 == 1'b0)tbr <= din ;end// Increment clockalways @(posedge rst or posedge clk16x)beginif (rst)clkdiv <= 4'b0000 ;else if (clk1x_enable == 1'b1)clkdiv <= clkdiv + 1 ;endassign clk1x = clkdiv[3] ;// Load TSR from TBR, shift TSRalways @(posedge rst or posedge clk1x)beginif (rst)tsr <= 8'h0 ;else if (no_bits_sent == 4'b0001)tsr <= tbr ;else if (no_bits_sent >= 4'b0010 && no_bits_sent < 4'b1010)begintsr[7:1] <= tsr[6:0] ;tsr[0] <= 1'b0 ;endend// Generate Manchester data from NRZassign mdo = tsr[7] ^ clk1x ;// Generate parityalways @(posedge rst or posedge clk1x)beginif (rst)parity <= 1'b0 ;else parity <= parity ^ tsr[7] ;end// Calculate number of bits sentalways @(posedge rst or posedge clk1x)beginif (rst)no_bits_sent <= 4'b0000 ;else if (clk1x_enable)no_bits_sent <= no_bits_sent + 1 ;// else if (no_bits_sent == 4'b1111)else if (clk1x_disable)no_bits_sent <= 4'b0000 ;endassign clk1x_disable = !clk1x_enable ;endmodule