///////////////////////////////////////////////////////////////////////////////////    File Name:  PatternGenerator.v//      Version:  2.2//         Date:  05/14/03//        Model:  Generate PRBS test patterns////      Company:  Xilinx, Inc.//  Contributor:  Mike Matera////   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,//                APPLICATION OR STANDARD, XILINX IS MAKING NO//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR//                PURPOSE.////                (c) Copyright 2003 Xilinx, Inc.//                All rights reserved./////////////////////////////////////////////////////////////////////////////////// // Summary:////   The PatternGenerator is used to generate a few PRBS patterns.// The patterns are selectable by the pattern_select_in port.//// The patterns are as follows:////    +---------+-------------+----------------------------------+//    | Value   | Length      | Description                      |//    +---------+-------------+----------------------------------+//    | 4'b0000 | n/a         | Clock Pattern (1010)             |//    | 4'b0001 | n/a         | 5 ones 5 zeros (0000011111)      |//    | 4'b0010 | n/a         | 10 ones 10 zeros                 |//    | 4'b0011 | 2^07 - 1    | 7-bit LFSR (not specd)           |//    | 4'b0100 | 2^09 - 1    | ITU-T-O.150 Section 5.1          |//    | 4'b0101 | 2^11 - 1    | ITU-T-O.150 Section 5.2          |//    | 4'b0110 | 2^15 - 1    | ITU-T-O.150 Section 5.3          |//    | 4'b0111 | 2^20 - 1    | ITU-T-O.150 Section 5.4          |//    | 4'b1000 | 2^20 - 1    | ITU-T-O.150 Section 5.5(Zero-Sup)|//    | 4'b1001 | 2^23 - 1    | ITU-T-O.150 Section 5.6          |//    | 4'b1010 | 2^29 - 1    | ITU-T-O.150 Section 5.7          |//    | 4'b1011 | 2^31 - 1    | ITU-T-O.150 Section 5.8          |//    | 4'b1100 | 2^32 - 1    | 32-bit LFSR (not specd)          |//    | 4'b1101 | n/a         | User Pattern                     |//    | 4'b1110 | n/a         | Reserved                         |//    | 4'b1111 | n/a         | Reserved                         |//    +---------+-------------+----------------------------------+////----------------------------------------------------------------`ifdef PATTERNGENERATOR `else `define PATTERNGENERATOR`timescale               100ps/10ps //-------------------------------------------------------------// // Constant Summary://// WITH_51     Defined enables ITU-T-O.150 Section 5.1// WITH_52     Defined enables ITU-T-O.150 Section 5.2// WITH_53     Defined enables ITU-T-O.150 Section 5.3// WITH_54     Defined enables ITU-T-O.150 Section 5.4// WITH_55     Defined enables ITU-T-O.150 Section 5.5// WITH_56     Defined enables ITU-T-O.150 Section 5.6// WITH_57     Defined enables ITU-T-O.150 Section 5.7// WITH_58     Defined enables ITU-T-O.150 Section 5.8// WITH_32BIT  Defined enables non specd 32-bit LFSR// WITH_7BIT   Defined enables non specd 7-bit LFSR//-------------------------------------------------------------module PatternGenerator(data_pipe0a_out, data_pipe0b_out, data_pipe1_out,                        advance_in, error_insert_pulse, pattern_select_in,                         reset_in, clock_in                        );   //-------------------------------------------------------------   //    // Port Summary:   //    // data_pipe0a_out[19:00] (synchronous: clock_in)   //    Pattern data from pipeline stage 0 (first stage).   //   // data_pipe0b_out[19:00] (synchronous: clock_in)   //    Pattern data from pipeline stage 0 (first stage).   //   // data_pipe1_out[19:00] (synchronous: clock_in)   //    Pattern data from pipeline stage 1 (second stage).   //   // advance_in (synchronous: clock_in)   //    Enable pin for the pattern generators.  data_out will   //    update every cycle this pin is held high.   //   // pattern_select_in[03:00] (synchronous: clock_in)   //    Selects which PRBS Pattern to use.   //   // reset_in (synchronous: clock_in)   //    Synchronous reset.    //   // clock_in (clock: buffered)   //    Pattern clock.   //   //-------------------------------------------------------------   output [19:00] data_pipe0a_out,data_pipe0b_out, data_pipe1_out;   input [03:00]  pattern_select_in;   input          advance_in, reset_in, clock_in;   input          error_insert_pulse;   parameter      CLOCK_SEL   = 4'b0000,                  CLOCK5_SEL  = 4'b0001,                  CLOCK10_SEL = 4'b0010,                  PRBS7_SEL   = 4'b0011,                  ITU_51_SEL  = 4'b0100,                  ITU_52_SEL  = 4'b0101,                            ITU_53_SEL  = 4'b0110,                  ITU_54_SEL  = 4'b0111,                  ITU_55_SEL  = 4'b1000,                  ITU_56_SEL  = 4'b1001,                  ITU_57_SEL  = 4'b1010,                  ITU_58_SEL  = 4'b1011,                  PRBS32_SEL  = 4'b1100,                  USER_SEL    = 4'b1101;   reg [19:00]    data_pipe0_out, data_pipe0a_out, data_pipe0b_out /* synthesis syn_preserve = 1 */;                      reg [19:00]    data_pipe1_out, data_select;   wire           PatternEnable, PreEnable;   assign PatternEnable = advance_in | PreEnable;   pipelined_reset pipe_control_comp     (      .pre_enable_out(PreEnable),       .reset_in(reset_in),       .clock_in(clock_in)      );   wire [19:00]   ITU_T_51, ITU_T_52, ITU_T_53, ITU_T_54, ITU_T_55, ITU_T_56, ITU_T_57, ITU_T_58;   wire [19:00]   PRBS_32BIT, PRBS_7BIT;   always @ (pattern_select_in or PRBS_32BIT or PRBS_7BIT or ITU_T_51 or ITU_T_52 or ITU_T_53 or ITU_T_54 or ITU_T_55 or ITU_T_56 or ITU_T_57 or ITU_T_58) begin      case (pattern_select_in)        CLOCK_SEL:   data_select <= 20'hAAAAA;        CLOCK5_SEL:  data_select <= 20'b00000111110000011111;        CLOCK10_SEL: data_select <= 20'b00000000001111111111;        PRBS7_SEL:   data_select <= PRBS_7BIT;        ITU_51_SEL:  data_select <= ITU_T_51;        ITU_52_SEL:  data_select <= ITU_T_52;        ITU_53_SEL:  data_select <= ITU_T_53;        ITU_54_SEL:  data_select <= ITU_T_54;        ITU_55_SEL:  data_select <= ITU_T_55;        ITU_56_SEL:  data_select <= ITU_T_56;        ITU_57_SEL:  data_select <= ITU_T_57;        ITU_58_SEL:  data_select <= ITU_T_58;        PRBS32_SEL:  data_select <= PRBS_32BIT;        USER_SEL:    data_select <= {`USER_PATTERN_H,`USER_PATTERN_L};        default:     data_select <= 20'hAAAAA;      endcase   end`ifdef WITH_32BIT   PRBS_32BIT pattern_32bit      (       .data_out(PRBS_32BIT),        .advance_in(PatternEnable),        .reset_in(reset_in),        .clock_in(clock_in)       );`else   assign PRBS_32BIT = 20'hAAAAA;`endif`ifdef WITH_51   PRBS_ITU_T_O150_51 pattern_51      (       .data_out(ITU_T_51),        .advance_in(PatternEnable),        .reset_in(reset_in),        .clock_in(clock_in)       );`else   assign ITU_T_51 = 20'hAAAAA;`endif`ifdef WITH_52   PRBS_ITU_T_O150_52 pattern_52      (       .data_out(ITU_T_52),        .advance_in(PatternEnable),        .reset_in(reset_in),        .clock_in(clock_in)       );`else   assign ITU_T_52 = 20'hAAAAA;`endif`ifdef WITH_53   PRBS_ITU_T_O150_53 pattern_53      (       .data_out(ITU_T_53),        .advance_in(PatternEnable),        .reset_in(reset_in),        .clock_in(clock_in)       );`else   assign ITU_T_53 = 20'hAAAAA;`endif`ifdef WITH_54   PRBS_ITU_T_O150_54 pattern_54      (       .data_out(ITU_T_54),        .advance_in(PatternEnable),        .reset_in(reset_in),        .clock_in(clock_in)       );`else   assign ITU_T_54 = 20'hAAAAA;`endif`ifdef WITH_55   PRBS_ITU_T_O150_55 pattern_55      (       .data_out(ITU_T_55),        .advance_in(PatternEnable),        .reset_in(reset_in),        .clock_in(clock_in)       );`else   assign ITU_T_55 = 20'hAAAAA;`endif`ifdef WITH_56   PRBS_ITU_T_O150_56 pattern_56      (       .data_out(ITU_T_56),        .advance_in(PatternEnable),        .reset_in(reset_in),        .clock_in(clock_in)       );`else   assign ITU_T_56 = 20'hAAAAA;`endif`ifdef WITH_57   PRBS_ITU_T_O150_57 pattern_57      (       .data_out(ITU_T_57),        .advance_in(PatternEnable),        .reset_in(reset_in),        .clock_in(clock_in)       );`else   assign ITU_T_57 = 20'hAAAAA;`endif`ifdef WITH_58   PRBS_ITU_T_O150_58 pattern_58      (       .data_out(ITU_T_58),        .advance_in(PatternEnable),        .reset_in(reset_in),        .clock_in(clock_in)       );`else   assign ITU_T_58 = 20'hAAAAA;`endif`ifdef WITH_7BIT   PRBS_7BIT pattern_7bit      (       .data_out(PRBS_7BIT),        .advance_in(PatternEnable),        .reset_in(reset_in),        .clock_in(clock_in)       );`else   assign PRBS_32BIT = 20'hAAAAA;`endif   always @ (posedge clock_in) begin      if (reset_in) begin         data_pipe0_out <= 0;         data_pipe0a_out <= 0;         data_pipe0b_out <= 0;      end else if (PatternEnable) begin           if (~error_insert_pulse) begin             data_pipe0_out <= data_select;             data_pipe0a_out <= data_select;             data_pipe0b_out <= data_select;           end else if (error_insert_pulse) begin             data_pipe0_out <= ~data_select;             data_pipe0a_out <= ~data_select;             data_pipe0b_out <= ~data_select;           end       end   end   always @ (posedge clock_in) begin      if (reset_in) begin         data_pipe1_out <= 0;      end else if (PatternEnable) begin          data_pipe1_out  <= data_pipe0_out;      end   endendmodulemodule pipelined_reset(pre_enable_out, reset_in, clock_in);   output pre_enable_out;   input  reset_in, clock_in;   reg [05:00] PipelineControl;   assign      pre_enable_out = PipelineControl[05];      always @ (posedge clock_in) begin      if (reset_in) PipelineControl <= 06'b111111;      else PipelineControl <= PipelineControl << 1;   endendmodule`endif