///////////////////////////////////////////////////////////////////////////////////    File Name:  MGTBoardBERT.v//      Version:  2.4//         Date:  2004-03-15//        Model:  Board Interface of the BERT//                This module implements a simple, user friendly demonstration//                of a Bit Error Rate test on the VirtexIIp MGT board.  Its//                purpose is to allow Xilinx customers to witness the MGT in//                action while using industry-standard test vectors to prove its//                performance.////      Company:  Xilinx, Inc.//  Contributor:  Mike Matera////   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,//                APPLICATION OR STANDARD, XILINX IS MAKING NO//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR//                PURPOSE.////                (c) Copyright 2003 Xilinx, Inc.//                All rights reserved./////////////////////////////////////////////////////////////////////////////////`ifdef MGTBOARDBERT `else`define MGTBOARDBERT`timescale               100ps/10psmodule MGTBoardBERT(serial_n_out, serial_p_out,                    serial_n_out_idle, serial_p_out_idle,                    serial_n_in, serial_p_in,                    serial_n_in_idle, serial_p_in_idle,                    bec_count_out,                    LEDs_out, DIP_switch_in, Push_buttons_in,                    rt_clock_in, BREF_CLK_P, BREF_CLK_N,                    total_frames_out, dropped_frames_out,error_factor_out, status,                    recovered_clocks_out                    );   //-------------------------------------------------------------   //   // Port Summary:   //   // serial_n_out   // serial_p_out (analog)   //    Must be connected to dedicated GT TX pads.   // serial_n_out_idle   // serial_p_out_idle (analog)   //    Must be connected to dedicated GT TX pads.   //   // serial_n_in   // serial_p_in (analog)   //    Must be connected to dedicated GT RX pads.   // serial_n_in_idle   // serial_p_in_idle (analog)   //    Must be connected to dedicated GT RX pads.   //   // bec_count_out (synchronous: clock_in)   //    Total number of bit errors.   //   // LEDS_out[15:00] (asynchronous)   //    Drives the MGT board's 16 LEDs.   //   // DIP_switch_in[35:00] (asynchronous)   //    Driven by the MGT board's 20 DIP switches.   //   // Push_buttons_in[03:00] (asynchronous)   //    Driven by the MGT board's 4 pushbutton switches.   //   // rt_clock_in (clock: unbuffered)   //    This clock controls the real-time circuits.   //   // BREF_CLK_{P,N} (clock: unbuffered)   //    LVDS Clock.  For the MGT.   //   // recovered_clocks_out (clock: buffered)   //    Buffered copy of the recovered clock used to time   //    the RX logic.   //   //-------------------------------------------------------------   // High Speed Signals:   output [01:00]  serial_n_out, serial_p_out;   output [01:00]  serial_n_out_idle, serial_p_out_idle;   input  [01:00]  serial_n_in, serial_p_in;   input  [01:00]  serial_n_in_idle, serial_p_in_idle;   // VirtexIIp MGT HID Signals:   output [15:00] LEDs_out;   input [35:00]  DIP_switch_in;   input [03:00]  Push_buttons_in;   // Clock Inputs   input          rt_clock_in;   inout  [3:0]   BREF_CLK_P;   inout  [3:0]   BREF_CLK_N;       output [02:0] recovered_clocks_out;   output [95:0] total_frames_out;   output [79:0] error_factor_out;   output [63:0] dropped_frames_out;   output [28:0] status;   output [63:0] bec_count_out;   wire bref_clock_in;   wire bref2_clock_in;   wire bref_clock_in_bot;   wire bref2_clock_in_bot;   wire bref_clock_in_i_0,bref2_clock_in_i_0;   wire bref_clock_in_i_1,bref2_clock_in_i_1;   wire ClockSelect_0,ClockSelect_1;   wire [15:00]   LEDs,LEDs_pwm;   wire [35:00]   DIPSwitches;   wire [03:00]   PushButtons;   wire           HumanEvent, MasterReset, ClockSelect;   wire [`DROPPED_FRAMES_MSB:00] dropped_frames_0, dropped_frames_1;   wire [`TOTAL_FRAMES_MSB:00]   total_frames_0, total_frames_1;   wire [`TOTAL_FRAMES_MSB:00]   error_factor_0, error_factor_1;   wire [03:00]  BERTReset;   wire [03:00]  PatternSelect1;   wire [03:00]  PatternSelect2;   wire [03:00]  LoopbackMode;   wire [03:00]  IdleLoopbackMode;   wire [01:00]  Link, Error, Abort, RECClock, TXDetect, DataDetect;   wire [01:00]  TXInhibit,IdleTXInhibit, MGTPowerDown,IdleMGTPowerDown;   wire [01:00]  ErrorInsert;   wire [03:00]  ProgDelay;   wire          MGTReset, MGTReset_bot, MGTReset_0, MGTReset_1;   wire          MGTClock;   wire          MGTClock_bot;   wire          MGTClock_0;   wire          MGTClock_1;   wire [01:00]  RECClock_buffered;   wire [31:00]  bec_count_out_0, bec_count_out_1;   wire          overflow_flag_0, overflow_flag_1;   wire [02:00]  bert_config_code;   reg  [1:0]     data_detect_r;   reg  [1:0]     link_r;   reg  [1:0]     abort_r;   wire          MGTClock_ok_0;   wire          MGTClock_ok_1;   wire          MGTClock_ok_0_i;   wire          MGTClock_ok_1_i;      wire [35:0]   control0_icon;   wire [40:00]  data_to_chipscope_0, data_to_chipscope_1;   assign bec_count_out = {bec_count_out_1, bec_count_out_0};    /////////////////////////////////////////////////////////////////////////////  // Note: Use IOBUFDS on BREFCLK inputs to enable switching on the BUFGMUX used in  // this BERT design while presently selected clock is stuck on High.  //  // According to Virtex-II Pro Platform FPGAs:Functional Description  // (Module 2, DS083-2), BUFGMUX description on page 39, "As long as the presently  // selected clock is High, any level changes of S has no effect."  // Therefore, if presently selected clock is stuck High, then clock switching  // using BUFGMUX will take no effect. The BERT design will not operate properly  // without a proper BREFCLK input.  //  // This likely happens when user leaves the BREFCLK input open (floating),  // and selects this clock input as default. A open circuit may produce a logic  // High on this clock input. Therefore, user can not switch to the other clock  // because of the BUFGMUX characteristic described above.  //  // To solve this problem, change the IBUFGDS (a differential clock input buffer)  // to an IOBUFDS (a 3-State differential signaling I/O buffer) in the BERT design,  // and connect the I input on IOBUFDS to Low, and T input on IOBUFDS to inverted  // reset signal. When reset is asserted, the IOBUFDS will force the O output to Low  // using the feedback path. The clock to the BUFGMUX will be Low so that switching  // on the BUFGMUX can take effect.  /////////////////////////////////////////////////////////////////////////////////  `ifdef USE_DIFF_CLK   IOBUFDS lvds_ibufg_crystal      (        .IO(BREF_CLK_P[0]/*BREF_CLK_P[0]*/),        .IOB(BREF_CLK_N[0]),        .I(1'b0),        .O(bref_clock_in),        .T(~MasterReset)      );              //   IBUFGDS_LVDS_25 lvds_ibufg_crystal        //      (        //       .I(BREF_CLK_P[0]), .IB(BREF_CLK_N[0]),        //       .O(bref_clock_in)        //       );   IOBUFDS lvds_ibufg_sma      (        .IO(BREF_CLK_P[1]),        .IOB(BREF_CLK_N[1]),        .I(1'b0),        .O(bref2_clock_in),        .T(~MasterReset)      );        //   IBUFGDS_LVDS_25 lvds_ibufg_sma        //      (        //       .I(BREF_CLK_P[1]), .IB(BREF_CLK_N[1]),        //       .O(bref2_clock_in)        //       );           `ifdef USER_USE_TOP_BOT_GT_yes     IOBUFDS lvds_ibufg_crystal_bot      (        .IO(BREF_CLK_P[2]),        .IOB(BREF_CLK_N[2]),        .I(1'b0),        .O(bref_clock_in_bot),        .T(~MasterReset)      );        //       IBUFGDS_LVDS_25 lvds_ibufg_crystal_bot        //      (        //       .I(BREF_CLK_P[2]), .IB(BREF_CLK_N[2]),        //       .O(bref_clock_in_bot)        //       );     IOBUFDS lvds_ibufg_sma_bot      (        .IO(BREF_CLK_P[3]),        .IOB(BREF_CLK_N[3]),        .I(1'b0),        .O(bref2_clock_in_bot),        .T(~MasterReset)      );              //      IBUFGDS_LVDS_25 lvds_ibufg_sma_bot        //      (        //       .I(BREF_CLK_P[3]), .IB(BREF_CLK_N[3]),        //       .O(bref2_clock_in_bot)        //       );    `else          assign bref_clock_in_bot = 1'b0;      assign bref2_clock_in_bot = 1'b0;           `endif     `else   IOBUF ibufg_crystal      (        .IO(BREF_CLK_P[0]),        .I(1'b0),        .O(bref_clock_in),        .T(~MasterReset)      );         //IBUFG  ibufg_crystal (.I(BREF_CLK_P[0]), .O(bref_clock_in));     IOBUF ibufg_sma      (        .IO(BREF_CLK_P[1]),        .I(1'b0),        .O(bref2_clock_in),        .T(~MasterReset)      );   //IBUFG  ibufg_sma (.I(BREF_CLK_P[1]), .O(bref2_clock_in));   `ifdef USER_USE_TOP_BOT_GT_yes     IOBUF ibufg_crystal_bot      (        .IO(BREF_CLK_P[2]),        .I(1'b0),        .O(bref_clock_in_bot),        .T(~MasterReset)      );          //IBUFG  ibufg_crystal_bot (.I(BREF_CLK_P[2]), .O(bref_clock_in_bot));     IOBUF ibufg_sma_bot      (        .IO(BREF_CLK_P[3]),        .I(1'b0),        .O(bref2_clock_in_bot),        .T(~MasterReset)      );          //IBUFG  ibufg_sma_bot (.I(BREF_CLK_P[3]), .O(bref2_clock_in_bot));         `else