///////////////////////////////////////////////////////////////////////////////////    File Name:  plb_ipif_slv_sram.v//      Version:  2.2//         Date:  05/14/03//        Model:  PLB Intellectual Property Interface (SRAM protocol) Module//                Implements a 32 Bit PLB IPIF module. Designed for 32//                Bit IP devices. Only responds to non-burst PLB transactions//                of one word or less.////      Company:  Xilinx, Inc.//  Contributor:  Systems Engineering Group////   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,//                APPLICATION OR STANDARD, XILINX IS MAKING NO//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR//                PURPOSE.////                (c) Copyright 2003 Xilinx, Inc.//                All rights reserved./////////////////////////////////////////////////////////////////////////////////module plb_ipif_slv_sram (  SYS_plbClk,  SYS_plbReset,// PLB Slave Interface  // Transfer Qualifiers Signals  // Inputs  PLB_PAValid,  PLB_busLock,  PLB_masterID,  PLB_RNW,  PLB_BE,  PLB_size,  PLB_type,  PLB_MSize,  PLB_compress,  PLB_guarded,  PLB_ordered,  PLB_lockErr,  PLB_abort,  PLB_ABus,  // Outputs  Sl_addrAck,  Sl_wait,  Sl_SSize,  Sl_rearbitrate,  Sl_MBusy,  Sl_MErr,  // Adress Pipelining Signals  // Inputs  PLB_SAValid,  PLB_rdPrim,  PLB_wrPrim,  // Write Data Bus Signals  // Inputs  PLB_wrDBus,  PLB_wrBurst,  // Outputs  Sl_wrDAck,  Sl_wrComp,  Sl_wrBTerm,  // Read Data Bus Signals  // Inputs  PLB_rdBurst,  // Outputs  Sl_rdDBus,  Sl_rdWdAddr,  Sl_rdDAck,  Sl_rdComp,  Sl_rdBTerm,  // IP Signals  // Ouput to IP Signals  Bus2IP_Clk,  Bus2IP_Reset,  Bus2IP_Addr,  Bus2IP_BE,  Bus2IP_Data,  Bus2IP_RdReq,  Bus2IP_SRAM_CE,  Bus2IP_WrReq,  // Input from IP Signals  IP2Bus_Data,  IP2Bus_Error,  IP2Bus_RdAck,  IP2Bus_Retry,  IP2Bus_ToutSup,  IP2Bus_WrAck  );   // Port Declarations ************************************************  input         SYS_plbClk;  input         SYS_plbReset;// PLB Slave Interface  // Transfer Qualifiers Signals  input         PLB_PAValid;  input         PLB_busLock;  input  [0:3]  PLB_masterID;  input         PLB_RNW;  input  [0:7]  PLB_BE;  input  [0:3]  PLB_size;  input  [0:2]  PLB_type;  input  [0:1]  PLB_MSize;  input         PLB_compress;  input         PLB_guarded;  input         PLB_ordered;  input         PLB_lockErr;  input         PLB_abort;  input  [0:31] PLB_ABus;  output        Sl_addrAck;  output        Sl_wait;  output [0:1]  Sl_SSize;  output        Sl_rearbitrate;  output [0:1] Sl_MBusy;  output [0:1] Sl_MErr;  // Adress Pipelining Signals  input         PLB_SAValid;  input         PLB_rdPrim;  input         PLB_wrPrim;  // Write Data Bus Signals  input  [0:63] PLB_wrDBus;  input         PLB_wrBurst;  output        Sl_wrDAck;  output        Sl_wrComp;  output        Sl_wrBTerm;  // Read Data Bus Signals  input         PLB_rdBurst;  output [0:63] Sl_rdDBus;  output [0:3]  Sl_rdWdAddr;  output        Sl_rdDAck;  output        Sl_rdComp;  output        Sl_rdBTerm;  // IP Signals  output        Bus2IP_Clk;  output        Bus2IP_Reset;  output [0:31] Bus2IP_Addr;  output [0:3]  Bus2IP_BE;  output [0:31] Bus2IP_Data;  output        Bus2IP_RdReq;  output        Bus2IP_SRAM_CE;  output        Bus2IP_WrReq;  input  [0:31] IP2Bus_Data /* synthesis syn_maxfan=100 */;  input         IP2Bus_Error /* synthesis syn_maxfan=100 */;  input         IP2Bus_RdAck /* synthesis syn_maxfan=100 */;  input         IP2Bus_Retry /* synthesis syn_maxfan=100 */;  input         IP2Bus_ToutSup /* synthesis syn_maxfan=100 */;  input         IP2Bus_WrAck /* synthesis syn_maxfan=100 */;// Signal Declarations ***********************************************  reg           access_valid;  wire   [0:31] base_addr_comp;  reg           busy;  reg    [0:3]  byte_enable32;  reg    [0:3]  masterID_hold;  reg    [0:31] Bus2IP_Addr;  reg    [0:3]  Bus2IP_BE;  reg    [0:31] Bus2IP_Data;  reg           Bus2IP_RdReq;  reg           Bus2IP_SRAM_CE;  reg           Bus2IP_WrReq;  wire   [0:1] Sl_MBusy;  reg    [0:1] Sl_MErr;  reg           Sl_rdComp;  reg           Sl_rdDAck;  reg    [0:63] Sl_rdDBus;  reg    [0:3]  Sl_rdWdAddr;  reg           Sl_wait;  reg           Sl_wrComp;  reg           Sl_wrDAck;  reg           word_addr2_sel;// Parameter Declarations ********************************************  parameter     LSB_ADDR_BIT = 23;  parameter     BASE_ADDR    = 32'h0000_0000;   // Main body of code *************************************************// Tie off unused PLB Signals  assign Sl_SSize[0:1] = {1'b0, access_valid};  assign Sl_rearbitrate = 1'b0;  assign Sl_wrBTerm = 1'b0;  assign Sl_rdBTerm = 1'b0;   // Decode PLB Accessassign base_addr_comp = BASE_ADDR;always @(posedge SYS_plbClk)  if (Sl_addrAck | PLB_abort | SYS_plbReset)    access_valid <= 1'b0;  else    access_valid <= (PLB_PAValid | PLB_SAValid) & // Address Request                    (PLB_size[0:3] == 4'b0000) &  // Non Burst Transfer                    ((PLB_BE[0:3] == 4'b0) | (PLB_BE[4:7] == 4'b0)) & // 1 word or less                    (PLB_type[0:2] == 3'b000) &   // Memory Type                    (PLB_ABus[0:LSB_ADDR_BIT] == base_addr_comp[0:LSB_ADDR_BIT]); // Addr Hit// Process Valid PLB transactionassign Sl_addrAck = PLB_PAValid & access_valid & ~busy;always @(posedge SYS_plbClk)  if (SYS_plbReset)    busy <= 1'b0;  else if (Sl_addrAck & ~PLB_abort)    busy <= 1'b1;  else if (Sl_rdComp | Sl_wrComp)    busy <= 1'b0;// Latch Transaction Qualifiers and drive info to IPassign Bus2IP_Clk = SYS_plbClk;assign Bus2IP_Reset = SYS_plbReset;always @(posedge SYS_plbClk)begin  byte_enable32 <= (PLB_BE[0:3] != 4'b0)? PLB_BE[0:3] : PLB_BE[4:7];  word_addr2_sel <= (PLB_BE[0:3] == 4'b0);  if (Sl_addrAck) begin    Bus2IP_Addr[0:28]  <= PLB_ABus[0:28];    Bus2IP_Addr[29]    <= word_addr2_sel;    Bus2IP_Addr[30:31] <= 2'b0;    Bus2IP_BE          <= byte_enable32;    Bus2IP_Data        <= (word_addr2_sel)? PLB_wrDBus[32:63] : PLB_wrDBus[0:31];    masterID_hold      <= PLB_masterID;  endendalways @(posedge SYS_plbClk)  if (SYS_plbReset) begin    Bus2IP_RdReq   <= 1'b0;    Bus2IP_SRAM_CE <= 1'b0;    Bus2IP_WrReq   <= 1'b0;  end  else if (Sl_addrAck & ~PLB_abort) begin    Bus2IP_RdReq   <= PLB_RNW;    Bus2IP_SRAM_CE <= 1'b1;    Bus2IP_WrReq   <= ~PLB_RNW;  end  else if (IP2Bus_RdAck | IP2Bus_WrAck) begin    Bus2IP_RdReq   <= 1'b0;    Bus2IP_SRAM_CE <= 1'b0;    Bus2IP_WrReq   <= 1'b0;  end// Process signals coming back from IP and send back response over PLBalways @(posedge SYS_plbClk)  if (SYS_plbReset) begin    Sl_rdComp     <= 1'b0;    Sl_wrComp     <= 1'b0;    Sl_rdDAck     <= 1'b0;    Sl_wrDAck     <= 1'b0;    Sl_rdDBus     <= 64'b0;    Sl_rdWdAddr   <= 4'b0;    Sl_MErr[0:1] <= 2'b0;    Sl_wait       <= 1'b0;  end  else begin    Sl_rdComp     <= IP2Bus_RdAck;    Sl_wrComp     <= IP2Bus_WrAck;    Sl_rdDAck     <= IP2Bus_RdAck;    Sl_wrDAck     <= IP2Bus_WrAck;    Sl_rdDBus     <= {64{IP2Bus_RdAck}} & {IP2Bus_Data,IP2Bus_Data};    Sl_rdWdAddr   <= {4{IP2Bus_RdAck}} & {Bus2IP_Addr[26:28],1'b0};    Sl_MErr[0]    <= IP2Bus_Error & (masterID_hold == 4'h0);    Sl_MErr[1]    <= IP2Bus_Error & (masterID_hold == 4'h1);    Sl_wait       <= IP2Bus_ToutSup;  end  assign Sl_MBusy[0]  = busy & (masterID_hold == 4'h0);  assign Sl_MBusy[1]  = busy & (masterID_hold == 4'h1); endmodule