///////////////////////////////////////////////////////////////////////////////////    File Name:  VirtexIIpBERT.v//      Version:  2.2//         Date:  05/14/03//        Model:  VirtexIIp MGT Bit Error Rate Tester.//                The VirtexIIpBERT contains the three modules necessary to//                implement a single-channel bit error rate test in Virtex-II Pro. //                Each channel under test should have one VirtexIIpBERT.////      Company:  Xilinx, Inc.//  Contributor:  Mike Matera////   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,//                APPLICATION OR STANDARD, XILINX IS MAKING NO//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR//                PURPOSE.////                (c) Copyright 2003 Xilinx, Inc.//                All rights reserved./////////////////////////////////////////////////////////////////////////////////`ifdef VIRTEXIIPBERT `else`define VIRTEXIIPBERT`timescale               100ps/10psmodule VirtexIIpBERT ( loopback_mode_in,idleloopback_mode_in,                       tx_inhibit_in, idletx_inhibit_in,                       powerdown_in, idlepowerdown_in,                       serial_n_out, serial_p_out,                       serial_n_out_idle, serial_p_out_idle,                       serial_n_in, serial_p_in,                       serial_n_in_idle, serial_p_in_idle,                       total_frames_out,                       dropped_frames_out,                       error_figure_out,                       bec_count_out,                       overflow_flag,                       error_insert,                       tx_detect_out, data_detect_out,                       link_out, error_out, abort_out,                       pattern_select_in,                       control_icon,                       ProgDelay,                       tx_reset_in, rx_reset_in,                       mgt_tx_reset_in, mgt_rx_reset_in,                       clock_direct0_in, clock_direct1_in,                       clock_select_in,                       clock_buffered_in,                       RECClock_buffered,                       recovered_clock_out,                       data_to_chipscope                       );   //-------------------------------------------------------------   //   // Port Summary:   //   // loopback_mode_in[01:00] (synchronous: clock_buffered_in)   //    Value of the GTs loopback mode input.   // idleloopback_mode_in[01:00] (synchronous: clock_buffered_in)   //    Value of the Idle GTs loopback mode input.   //   // tx_inhibit_in (synchronous: clock_buffered_in)   //    Prevents the GT from transmitting data.   // idletx_inhibit_in (synchronous: clock_buffered_in)   //    Prevents the IdleGT from transmitting data.   //   // powerdown_in (asynchronous)   //    Puts the GT into powerdown mode.   // idlepowerdown_in (asynchronous)   //    Puts the Idle GT into powerdown mode.   //   // serial_n_out   // serial_p_out (analog)   //    Must be connected to dedicated GT TX pads.   // serial_n_out_idle   // serial_p_out_idle (analog)   //    Must be connected to dedicated GT TX pads.   //   // serial_n_in   // serial_p_in (analog)   //    Must be connected to dedicated GT RX pads.   // serial_n_in_idle   // serial_p_in_idle (analog)   //    Must be connected to dedicated GT RX pads.   //   // total_frames_out[`TOTAL_FRAMES_MSB:00] (synchronous: clock_in)   //    Total frames received.   //   // dropped_frames_out[`DROPPED_FRAMES_MSB:00] (synchronous: clock_in)   //    Total frames received with error.   //   // error_figure_out[`TOTAL_FRAMES_MSB:00] (synchronous: clock_in)   //    Shortest interval between consecutive errors.  This   //    number is important for good calculation of a bit   //    error rate.   //   // bec_count_out (synchronous: clock_in)   //    Total number of bit errors.   //   // overflow_flag (synchronous: clock_in)   //    Overflow flag indicating the overflow of bit error counter.   //   // tx_detect_out (synchronous: clock_buffered_in)   //    High when the transmitters preamble sequence is detected   //    by the receiver.   //   // data_detect_out (synchronous: clock_buffered_in)   //    High when the receiver detects a PRBS sequence.  This   //    signal is generated by the MGTs low-level comma detect   //    signal.   //   // link_out (synchronous: clock_buffered_in)   //    High if GigabitBER_RX has detected a GigbitBER_TX.   //   // error_out (synchronous: clock_buffered_in)   //    High if GigabitBER_RX has detected an error.   //   // abort_out (synchronous: clock_buffered_in)   //    High if GigabitBER_RX has aborted operation due to errors.   //   // pattern_select_in[03:00] (synchronous: clock_buffered_in)   //    Selects which PRBS Pattern to use.   //   // ProgDelay[03:00] (synchronous: clock_buffered_in)   //    Selects the delay in tx_data_in of noise source mgts.   //   // tx_reset_in (synchronous: clock_buffered_in)   //    Synchronous Transmitter reset.   //   // rx_reset_in (synchronous: clock_buffered_in)   //    Synchronous Receiver reset.   //   // mgt_tx_reset_in (asynchronous)   //    Resets the MGT Transmitter.   //   // mgt_rx_reset_in (asynchronous)   //    Resets the MGT Reciever.   //   // clock_direct0_in (clock: unfuffered)   //    One reference clock for the GT:  Must come directly from IO.   //   // clock_direct1_in (clock: unfuffered)   //    One reference clock for the GT:  Must come directly from IO.   //   // clock_select_in (asynchronous)   //    Selectes which reference clock to use.   //    0: use clock_direct0_in   //    1: use clock_direct1_in.   //   // clock_buffered_in (clock: buffered)   //    Clock for the digital TX and RX portions of the GT.   //   // recovered_clock_out (clock: buffered (output))   //    Buffered copy of the recovered clock.   //   //-------------------------------------------------------------   output [`DROPPED_FRAMES_MSB:00] dropped_frames_out;   output [`TOTAL_FRAMES_MSB:00]   total_frames_out, error_figure_out;   output                          serial_n_out, serial_p_out, link_out, tx_detect_out,                                   data_detect_out, error_out, abort_out, recovered_clock_out,                                   serial_n_out_idle, serial_p_out_idle;   output [31:00]                  bec_count_out;   output                          overflow_flag;   output                          RECClock_buffered;   input                           error_insert;      input [35:00]                   control_icon;   input [03:00]                   pattern_select_in;   input [03:00]                   ProgDelay;   input [01:00]                   loopback_mode_in;   input [01:00]                   idleloopback_mode_in;   input                           tx_inhibit_in,idletx_inhibit_in,                                    serial_n_in, serial_p_in,                                   clock_direct0_in, clock_direct1_in,                                   clock_select_in, clock_buffered_in,                                   tx_reset_in, rx_reset_in,                                   mgt_tx_reset_in, mgt_rx_reset_in,                                   powerdown_in,idlepowerdown_in,                                   serial_n_in_idle,serial_p_in_idle;   output [40:0]                   data_to_chipscope;      wire [19:00]                    tx_data_out, mgt_data_out,tx_data_out_delayed_i;   reg  [19:00]                    tx_data_out_delayed;   wire                            CommaDetect, CommaDetect__synch, CommaAlign, CommaAlign__synch;   wire                            RECClock;   wire [31:00]                    bec_count_out;   wire                            overflow_flag;   wire                            error_insert_pulse;   reg  [03:00]                    ProgDelay_i;   wire [40:00]                    data_to_chipscope;      assign                          tx_detect_out = CommaAlign;   assign                          data_detect_out = CommaDetect;   assign                          recovered_clock_out = RECClock;   // attribute CLOCK_SIGNAL: RECClock_buffered;      BUFG RECCLK_buffered (.I(RECClock), .O(RECClock_buffered));   RisingEdgeDetect edge_comp     (      .rising_edge_out(CommaAlign__synch),      .sig_in(CommaAlign),      //.clock_in(RECClock_buffered)       .clock_in(RECClock)      );   LevelDetect comma_comp      (      .sig_level_out(CommaDetect__synch),       .sig_in(CommaDetect),       .clock_in(RECClock_buffered)      );   EdgeDetect error_comp     (      .edge_out(error_insert_pulse),      .sig_in(error_insert),      .clock_in(clock_buffered_in)       );      GigabitBER_TX tx_comp     (      .data_out(tx_data_out),      .reset_in(tx_reset_in),      .error_insert_pulse(error_insert_pulse),      .pattern_select_in(pattern_select_in),      .clock_in(clock_buffered_in)      );   GigabitBER_RX rx_comp     (       .data_in(mgt_data_out),       .comma_detect_in(CommaDetect__synch),       .en_comma_align_out(CommaAlign),       .total_frames_out(total_frames_out),       .dropped_frames_out(dropped_frames_out),       .error_figure_out(error_figure_out),       .search_out(/*Not Used*/),       .link_out(link_out),       .error_out(error_out),       .abort_out(abort_out),       .bec_count_out(bec_count_out),       .overflow_flag(overflow_flag),       .pattern_select_in(pattern_select_in),              .data_to_chipscope(data_to_chipscope),       .reset_in(rx_reset_in),       .clock_in(RECClock_buffered)       );   MGT_BERT_4 mgt_comp     (      // MGT Clocks:      .ref_clock0_in(clock_direct0_in), .ref_clock1_in(clock_direct1_in),      .ref_clock_select_in(clock_select_in),      .tx_clock_in(clock_buffered_in), .rx_clock_in(RECClock_buffered), .rec_clock_out(RECClock),      // MGTParallel Data:      .tx_parallel_data_in(tx_data_out),      .rx_parallel_data_out(mgt_data_out),      // MGT Serial Data:      .serial_n_out(serial_n_out), .serial_p_out(serial_p_out),      .serial_n_in(serial_n_in), .serial_p_in(serial_p_in),      // MGT Control Signals (TX Domain):      .loopback_mode_in(loopback_mode_in), .tx_reset_in(mgt_tx_reset_in), .tx_inhibit_in(tx_inhibit_in),      // MGT Control Signals (RX Domain):      .rx_reset_in(mgt_rx_reset_in), .rx_comma_detect_out(CommaDetect), .rx_realign_out(/*Not Used*/),      // MGT Control Signals (Asynchronous):      .powerdown_in(powerdown_in), .en_p_comma_align_in(CommaAlign__synch)      );    /////////////////////////////////////////////////    // Optional Idle MGT    /////////////////////////////////////////////////  `ifdef USER_USE_MGT_IDLE_yes      // Instantiate Programmable Delay Module    always @(ProgDelay or tx_data_out or tx_data_out_delayed_i) begin          if (ProgDelay == 4'b0000)             tx_data_out_delayed = tx_data_out;          else            tx_data_out_delayed = tx_data_out_delayed_i;    end    DELAY_SRL mdelay_comp          (            .clk(clock_buffered_in),            .enable(1'b1),            .dataIn(tx_data_out),            .result(tx_data_out_delayed_i),            .addr(ProgDelay - 1) //programmable delay          );      // Instantiate Idle MGT module to generate noise     MGT_BERT_4 mgt_comp_idle     (      .ref_clock0_in(clock_direct0_in), .ref_clock1_in(clock_direct1_in),      .ref_clock_select_in(clock_select_in),      .tx_clock_in(clock_buffered_in),      .rx_clock_in(clock_buffered_in),       .tx_parallel_data_in(tx_data_out_delayed),      .serial_n_out(serial_n_out_idle), .serial_p_out(serial_p_out_idle),      .serial_n_in(serial_n_in_idle), .serial_p_in(serial_p_in_idle),      .loopback_mode_in(idleloopback_mode_in),      .tx_reset_in(mgt_tx_reset_in),      .tx_inhibit_in(idletx_inhibit_in),      .rx_reset_in(mgt_rx_reset_in ),      .powerdown_in(idlepowerdown_in)     );    `else          assign serial_n_out_idle = 1'b0;      assign serial_p_out_idle = 1'b0;   `endifendmodulemodule DELAY_SRL(clk, enable, dataIn, result, addr);        input clk, enable;        input  [19:0] dataIn;        input  [3:0] addr;        output [19:0] result;        reg [19:0] regBank[15:0];        integer i;        always @(posedge clk) begin          if (enable == 1) begin            for (i=15; i>0; i=i-1) begin              regBank[i] <= regBank[i-1];            end            regBank[0] <= dataIn;         end        end        assign result = regBank[addr]; endmodule `endif