///////////////////////////////////////////////////////////////////////////////////    File Name:  PatternFollower.v//      Version:  2.2//         Date:  05/14/03//        Model:  A state machine to accomplish pattern locking.//                The PatternFollower implements the majority of the logic in//                GigabitBER_RX.  It's duty is to provide information on the//                correctness of the incoming data stream.////      Company:  Xilinx, Inc.//  Contributor:  Mike Matera////   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,//                APPLICATION OR STANDARD, XILINX IS MAKING NO//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR//                PURPOSE.////                (c) Copyright 2003 Xilinx, Inc.//                All rights reserved./////////////////////////////////////////////////////////////////////////////////`ifdef PATTERNFOLLOWER `else`define PATTERNFOLLOWER`timescale               100ps/10psmodule PatternFollower( data_in, bit_error_out, errored_bits,                        locked_out, distress_out, abort_out, armed_out,                        pattern_select_in, reset_in, clock_in, data_to_chipscope                        );   //-------------------------------------------------------------   //   // Port Summary:   //   // data_in[19:00] (synchronous: clock_in)   //    Data from the MGT.   //   // locked_out (synchronous: clock_in)   //    High indicating the PatternFollower has established a link.   //   // distress_out (synchronous: clock_in)   //    High indicating a bit error has occoured and the link is   //    considered unstable.  If a second consecutive error occours   //    the link will be aborted.   //   // abort_out (synchronous: clock_in)   //    High when the PatternFollower has aborted the link   //    due to bit errors.   //   // armed_out (synchronous: clock_in)   //    High indicating the PatternFollower is waiting to   //    establish link.   //   // bit_error_out (synchronous: clock_in)   //    High indicating a bit error has occoured. (Pipelined one cycle)   //   // errored_bits (synchronous: clock_in)   //    Total number of bit errors.   //   // pattern_select_in[03:00] (synchronous: clock_in)   //    Selects which PRBS Pattern to use.   //   // reset_in (synchronous: clock_in)   //    Reset the PatternFollower   //   // clock_in (clock: buffered)   //    Reciever clock.  This clock must also be connected to   //    RXUSRCLK on the MGT.   //   //-------------------------------------------------------------   input [19:00] data_in;   input [03:00] pattern_select_in;   output          locked_out, distress_out, abort_out, armed_out,                   bit_error_out;   output [31:00]  errored_bits;   input         reset_in, clock_in;      output [40:00] data_to_chipscope;   parameter     RESET_STATE     = 5'b00001,                 ARM_STATE       = 5'b00010,                 LOCKED_STATE    = 5'b00100,                 DISTRESS_STATE  = 5'b01000,                 ABORT_STATE     = 5'b10000;   reg [19:00]   data_in__pipe0;   reg [04:00]   MachineState, MachineState__next;   reg           FrameError_del;   reg           FrameError_del1;   reg           bit_error_out;   reg [19:00]   error_cmp;   reg [31:00]   errored_bits, errored_bits_a, errored_bits_b;   reg           abort_del, distress_del, locked_del, arm_del, reset_del;   reg           abort_del1, distress_del1, locked_del1, arm_del1, reset_del1;   wire          abort_bit, distress_bit, locked_bit, arm_bit, reset_bit;   assign {abort_bit, distress_bit, locked_bit, arm_bit, reset_bit} = MachineState;   wire [19:00]  expected_data__pipe0a, expected_data__pipe0b, expected_data__pipe1;   wire          PatternAdvance;   wire          Go, Continue;   wire          FrameError;   assign locked_out     = locked_del1;   assign distress_out   = distress_del1;   assign abort_out      = abort_del1;   assign armed_out      = arm_del1;   assign data_to_chipscope[40:00] = {data_in__pipe0[19:00], expected_data__pipe0a[19:00], locked_bit};   `ifdef SERDES_10B   assign Go             = (expected_data__pipe1[09:00] == data_in__pipe0[09:00]);   assign Continue       = (expected_data__pipe0b[09:00] == data_in__pipe0[09:00]);`else   assign Go             = (expected_data__pipe1 == data_in__pipe0);   assign Continue       = (expected_data__pipe0b == data_in__pipe0);`endif   assign PatternAdvance = locked_bit | distress_bit | abort_bit;   assign FrameError     = ~Continue & PatternAdvance;   PatternGenerator expected_comp     (      .data_pipe0a_out(expected_data__pipe0a),      .data_pipe0b_out(expected_data__pipe0b),      .data_pipe1_out(expected_data__pipe1),      .error_insert_pulse(1'b0),      .pattern_select_in(pattern_select_in),      .advance_in(PatternAdvance), .reset_in(reset_bit),      .clock_in(clock_in)      );   always @ (MachineState or Go or Continue) begin      MachineState__next <= MachineState;      case (MachineState)        RESET_STATE:     MachineState__next <= ARM_STATE;        ARM_STATE:       if (Go) MachineState__next <= LOCKED_STATE;        LOCKED_STATE:    if (~Continue) MachineState__next <= DISTRESS_STATE;        DISTRESS_STATE:                         begin                            if (Continue) MachineState__next <= LOCKED_STATE;                            else MachineState__next <= ABORT_STATE;                         end        ABORT_STATE:     MachineState__next <= ABORT_STATE;        default:         MachineState__next <= RESET_STATE;      endcase   end   always @ (posedge clock_in) begin      if (reset_in) MachineState <= RESET_STATE;      else MachineState <= MachineState__next;   end   always @ (posedge clock_in)   begin      if (reset_in)       begin          error_cmp      <= 20'd0;          errored_bits   <= 32'd0;          errored_bits_a <= 32'd0;          errored_bits_b <= 32'd0;      end      else       begin          error_cmp      <= data_in__pipe0 ^ expected_data__pipe0a;          errored_bits_a <= error_cmp[19] + error_cmp[18] + error_cmp[17] + error_cmp[16] + error_cmp[15] +                             error_cmp[14] + error_cmp[13] + error_cmp[12] + error_cmp[11] + error_cmp[10];            errored_bits_b <= error_cmp[9] + error_cmp[8] + error_cmp[7] + error_cmp[6] + error_cmp[5] +                             error_cmp[4] + error_cmp[3] + error_cmp[2] + error_cmp[1] + error_cmp[0];                     errored_bits   <= errored_bits_a + errored_bits_b;      end   end   always @ (posedge clock_in) begin      data_in__pipe0  <= data_in;      FrameError_del   <= FrameError;      FrameError_del1  <= FrameError_del;      bit_error_out  <= FrameError_del1;      locked_del     <= locked_bit;      locked_del1    <= locked_del;      distress_del   <= distress_bit;      distress_del1  <= distress_del;      abort_del      <= abort_bit;      abort_del1      <= abort_del;      arm_del        <= arm_bit;      arm_del1       <= arm_del;   endendmodule`endif