library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rs232_receiver2 is 
	port(Clk:in Bit;
	Reset:in Bit;--AsynchronousReset
	RxIn:in Bit;--Serialdatain
	RxOut: out Bit_Vector(7 downto 0));--Lastreceiveddata,end rs232_receiver2;--Bit0isLSB

architecture RTL of rs232_receiver2 isconstant Count9600: Integer:=2604;
constant baud8count: Integer:=326;
constant InitRxReg: Bit_Vector:="1111111110";--Init.patternsignal RxInSync: Bit:='1'; --SynchronisedRxsignal baud8tick: Bit:='0';

begin --Architecture RTL of RS232_Receive
baud8: process(Clk)
variable count8: Integer range 0 to 511:=0;
begin
	if Clk'Event and Clk='1' then
		if(count8>=baud8count) then
			baud8tick<= not baud8tick;
			count8:=0;
		else
			count8:=count8+1;
		end if;
	end if;
end process baud8;

SyncRxIn: process(baud8tick,Reset)begin 
	if Reset = '1' then --Asynchron.reset
		RxInSync <= '1';	elsif baud8tick'event and baud8tick='1' then --Rising Clk edge 
		RxInSync<=RxIn;
	end if;end process SyncRxIn;

Rs232: process(Clk,Reset)
variable BaudCount: 	Integer range 0 to 4095;variable Sample: 		Bit; --For bit samplevariable DelaySample: 	Bit; --To detect edgevariable RxReg: 		Bit_Vector(9 downto 0); --10 bit shift register

begin 
	if Reset = '1' then --Asynchron.reset,
		BaudCount := 0; --initialize all 
		Sample := '0'; --values 
		DelaySample := '0';
		RxReg := InitRxReg;
		RxOut <= "00000000";	elsif Clk'Event and Clk='1' then --Rising Clk edge
	--Wait for RxInSync to be 0, i.e. the start bit in the serial
	--inputstream.		if RxInSync='1' and RxReg(0)='0' then 
		--Waiting for the start bit; initialise values 
		BaudCount:=0;
		Sample:='0';
		RxReg:=InitRxReg;
		elsif(BaudCount>=Count9600) then
			--The counter has reached half a bit period(assuming that
			--Clk runs at 10MHz); reset counter and toggle the Sample
			--signal(the exact bit rates are 1220,2441,4882&9765)
			BaudCount:=0;
			Sample:= not Sample;
		else --RxInSync=