?? led2.fit.rpt
字號:
Fitter report for LED2
Sun Mar 01 19:06:19 2009
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Pin-Out File
5. Fitter Resource Usage Summary
6. Input Pins
7. Output Pins
8. I/O Bank Usage
9. All Package Pins
10. Output Pin Default Load For Reported TCO
11. Fitter Resource Utilization by Entity
12. Delay Chain Summary
13. Control Signals
14. Global & Other Fast Signals
15. Non-Global High Fan-Out Signals
16. Interconnect Usage Summary
17. LAB Logic Elements
18. LAB-wide Signals
19. LAB Signals Sourced
20. LAB Signals Sourced Out
21. LAB Distinct Inputs
22. Fitter Device Options
23. Advanced Data - General
24. Advanced Data - Placement Preparation
25. Advanced Data - Placement
26. Advanced Data - Routing
27. Fitter Messages
28. Fitter Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-----------------------------------------+
; Fitter Status ; Successful - Sun Mar 01 19:06:19 2009 ;
; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name ; LED2 ;
; Top-level Entity Name ; LED2 ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 34 / 240 ( 14 % ) ;
; Total pins ; 14 / 80 ( 18 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+-----------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EPM240T100C5 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Always Enable Input Buffers ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing ; Off ; Off ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Delay Chains ; On ; On ;
; Perform Physical Synthesis for Combinational Logic ; Off ; Off ;
; Perform Register Duplication ; Off ; Off ;
; Perform Register Retiming ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Auto ; Auto ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Stop After Congestion Map Generation ; Off ; Off ;
; Use smart compilation ; Off ; Off ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/張永順/FPGA/助學活動/LED2/LED2.pin.
+-----------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+-------------------+
; Resource ; Usage ;
+---------------------------------------------+-------------------+
; Total logic elements ; 34 / 240 ( 14 % ) ;
; -- Combinational with no register ; 18 ;
; -- Register only ; 8 ;
; -- Combinational with a register ; 8 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 13 ;
; -- 3 input functions ; 4 ;
; -- 2 input functions ; 8 ;
; -- 1 input functions ; 4 ;
; -- 0 input functions ; 5 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 27 ;
; -- arithmetic mode ; 7 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 5 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 16 / 240 ( 7 % ) ;
; Total LABs ; 8 / 24 ( 33 % ) ;
; Logic elements in carry chains ; 8 ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 14 / 80 ( 18 % ) ;
; -- Clock pins ; 1 ;
; Global signals ; 1 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; Global clocks ; 1 / 4 ( 25 % ) ;
; Average interconnect usage ; 3% ;
; Peak interconnect usage ; 3% ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 16 ;
; Highest non-global fan-out signal ; Equal0~89 ;
; Highest non-global fan-out ; 16 ;
; Total fan-out ; 116 ;
; Average fan-out ; 2.42 ;
+---------------------------------------------+-------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; CLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; D0 ; 38 ; 1 ; 4 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; D1 ; 39 ; 1 ; 5 ; 0 ; 3 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; D2 ; 40 ; 1 ; 5 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
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