module	LED2(a,b,c,d,e,f,g,CS1,CS2,D3,D2,D1,D0,CLK);
output		a,b,c,d,e,f,g,CS1,CS2;
input		D3,D2,D1,D0,CLK;
reg			a,b,c,d,e,f,g,CS1,CS2;
reg     	r3,r2,r1,r0;
reg[7:0]	buffer;
always	@(posedge CLK)
	begin
		r3 =~D3;
		r2 =~D2;
		r1 =~D1;
		r0 =~D0;
		buffer = buffer+1;
		if(buffer == 8'd0)
			begin
				if({r3,r2,r1,r0} > 9)
					begin
						CS1=1'b1;
						CS2=1'b0;
						{a,b,c,d,e,f,g}=7'b0110000;	
					end
				else
					begin
						CS1=1'b1;
						CS2=1'b0;
						{a,b,c,d,e,f,g}=7'b1111110;	
					end			
			end
		else if(buffer == 8'd128)
			begin
				CS1=1'b0;
				CS2=1'b1;
				case({r3,r2,r1,r0})
				4'd0: {a,b,c,d,e,f,g}=7'b1111110;
				4'd1: {a,b,c,d,e,f,g}=7'b0110000;
				4'd2: {a,b,c,d,e,f,g}=7'b1101101;
				4'd3: {a,b,c,d,e,f,g}=7'b1111001;
				4'd4: {a,b,c,d,e,f,g}=7'b0110011;
				4'd5: {a,b,c,d,e,f,g}=7'b1011011;		
				4'd6: {a,b,c,d,e,f,g}=7'b1011111;
				4'd7: {a,b,c,d,e,f,g}=7'b1110000;
				4'd8: {a,b,c,d,e,f,g}=7'b1111111;
				4'd9: {a,b,c,d,e,f,g}=7'b1111011;
				4'd10: {a,b,c,d,e,f,g}=7'b1111110;
				4'd11: {a,b,c,d,e,f,g}=7'b0110000;
				4'd12: {a,b,c,d,e,f,g}=7'b1101101;
				4'd13: {a,b,c,d,e,f,g}=7'b1111001;
				4'd14: {a,b,c,d,e,f,g}=7'b0110011;
				4'd15: {a,b,c,d,e,f,g}=7'b1011011;
				default: {a,b,c,d,e,f,g}=7'b1111110;
				endcase
			end

	end
endmodule