-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L34Q is a~reg0 at LC_X4_Y2_N8
--operation mode is normal

A1L34Q_lut_out = A1L64 & (A1L32 & (!A1L57) # !A1L32 & A1L33) # !A1L64 & (!A1L57);
A1L34Q = DFFEAS(A1L34Q_lut_out, GLOBAL(CLK), VCC, , A1L64, , , , );


--A1L45Q is b~reg0 at LC_X4_Y2_N5
--operation mode is normal

A1L45Q_lut_out = A1L58 # !A1L32 & A1L64;
A1L45Q = DFFEAS(A1L45Q_lut_out, GLOBAL(CLK), VCC, , A1L64, , , , );


--A1L48Q is c~reg0 at LC_X4_Y2_N6
--operation mode is normal

A1L48Q_lut_out = !A1L32 & A1L64 # !A1L47;
A1L48Q = DFFEAS(A1L48Q_lut_out, GLOBAL(CLK), VCC, , A1L64, , , , );


--A1L50Q is d~reg0 at LC_X5_Y2_N4
--operation mode is normal

A1L50Q_lut_out = A1L32 & (!A1L59) # !A1L32 & (A1L64 & A1L33 # !A1L64 & (!A1L59));
A1L50Q = DFFEAS(A1L50Q_lut_out, GLOBAL(CLK), VCC, , A1L64, , , , );


--A1L52Q is e~reg0 at LC_X5_Y2_N7
--operation mode is normal

A1L52Q_lut_out = A1L32 & (A1L60) # !A1L32 & (A1L64 & (A1L33) # !A1L64 & A1L60);
A1L52Q = DFFEAS(A1L52Q_lut_out, GLOBAL(CLK), VCC, , A1L64, , , , );


--A1L54Q is f~reg0 at LC_X5_Y2_N1
--operation mode is normal

A1L54Q_lut_out = A1L32 & (!A1L61) # !A1L32 & (A1L64 & A1L33 # !A1L64 & (!A1L61));
A1L54Q = DFFEAS(A1L54Q_lut_out, GLOBAL(CLK), VCC, , A1L64, , , , );


--A1L56Q is g~reg0 at LC_X4_Y2_N0
--operation mode is normal

A1L56Q_lut_out = !A1L62 & (A1L32 # !A1L64);
A1L56Q = DFFEAS(A1L56Q_lut_out, GLOBAL(CLK), VCC, , A1L64, , , , );


--A1L3Q is CS1~reg0 at LC_X4_Y2_N3
--operation mode is normal

A1L3Q_lut_out = A1L64 & !A1L32;
A1L3Q = DFFEAS(A1L3Q_lut_out, GLOBAL(CLK), VCC, , A1L64, , , , );


--A1L33 is a~142 at LC_X5_Y2_N2
--operation mode is normal

A1L33 = D3 # D1 & D2;


--A1L10 is add~121 at LC_X3_Y2_N0
--operation mode is arithmetic

A1L10 = !buffer[0];

--A1L11 is add~123 at LC_X3_Y2_N0
--operation mode is arithmetic

A1L11_cout_0 = buffer[0];
A1L11 = CARRY(A1L11_cout_0);

--A1L12 is add~123COUT1_168 at LC_X3_Y2_N0
--operation mode is arithmetic

A1L12_cout_1 = buffer[0];
A1L12 = CARRY(A1L12_cout_1);


--A1L13 is add~126 at LC_X3_Y2_N1
--operation mode is arithmetic

A1L13 = buffer[1] $ A1L11;

--A1L14 is add~128 at LC_X3_Y2_N1
--operation mode is arithmetic

A1L14_cout_0 = !A1L11 # !buffer[1];
A1L14 = CARRY(A1L14_cout_0);

--A1L15 is add~128COUT1_170 at LC_X3_Y2_N1
--operation mode is arithmetic

A1L15_cout_1 = !A1L12 # !buffer[1];
A1L15 = CARRY(A1L15_cout_1);


--A1L16 is add~131 at LC_X3_Y2_N2
--operation mode is arithmetic

A1L16 = buffer[2] $ !A1L14;

--A1L17 is add~133 at LC_X3_Y2_N2
--operation mode is arithmetic

A1L17_cout_0 = buffer[2] & !A1L14;
A1L17 = CARRY(A1L17_cout_0);

--A1L18 is add~133COUT1_172 at LC_X3_Y2_N2
--operation mode is arithmetic

A1L18_cout_1 = buffer[2] & !A1L15;
A1L18 = CARRY(A1L18_cout_1);


--A1L19 is add~136 at LC_X3_Y2_N3
--operation mode is arithmetic

A1L19 = buffer[3] $ A1L17;

--A1L20 is add~138 at LC_X3_Y2_N3
--operation mode is arithmetic

A1L20_cout_0 = !A1L17 # !buffer[3];
A1L20 = CARRY(A1L20_cout_0);

--A1L21 is add~138COUT1_173 at LC_X3_Y2_N3
--operation mode is arithmetic

A1L21_cout_1 = !A1L18 # !buffer[3];
A1L21 = CARRY(A1L21_cout_1);


--A1L63 is rtl~93 at LC_X3_Y2_N8
--operation mode is normal

A1L63 = !A1L19 & !A1L13 & !A1L10 & !A1L16;


--A1L22 is add~141 at LC_X3_Y2_N4
--operation mode is arithmetic

A1L22 = buffer[4] $ !A1L20;

--A1L23 is add~143 at LC_X3_Y2_N4
--operation mode is arithmetic

A1L23 = A1L24;


--A1L26 is add~146 at LC_X3_Y2_N5
--operation mode is arithmetic

A1L26_carry_eqn = (!A1L23 & GND) # (A1L23 & VCC);
A1L26 = buffer[5] $ A1L26_carry_eqn;

--A1L27 is add~148 at LC_X3_Y2_N5
--operation mode is arithmetic

A1L27_cout_0 = !A1L23 # !buffer[5];
A1L27 = CARRY(A1L27_cout_0);

--A1L28 is add~148COUT1_175 at LC_X3_Y2_N5
--operation mode is arithmetic

A1L28_cout_1 = !A1L23 # !buffer[5];
A1L28 = CARRY(A1L28_cout_1);


--A1L29 is add~151 at LC_X3_Y2_N6
--operation mode is arithmetic

A1L29_carry_eqn = (!A1L23 & A1L27) # (A1L23 & A1L28);
A1L29 = buffer[6] $ !A1L29_carry_eqn;

--A1L30 is add~153 at LC_X3_Y2_N6
--operation mode is arithmetic

A1L30_cout_0 = buffer[6] & !A1L27;
A1L30 = CARRY(A1L30_cout_0);

--A1L31 is add~153COUT1_177 at LC_X3_Y2_N6
--operation mode is arithmetic

A1L31_cout_1 = buffer[6] & !A1L28;
A1L31 = CARRY(A1L31_cout_1);


--A1L64 is rtl~94 at LC_X4_Y2_N4
--operation mode is normal

A1L64 = A1L63 & !A1L22 & !A1L29 & !A1L26;


--A1L32 is add~156 at LC_X3_Y2_N7
--operation mode is normal

A1L32_carry_eqn = (!A1L23 & A1L30) # (A1L23 & A1L31);
A1L32 = A1L32_carry_eqn $ buffer[7];


--A1L57 is reduce_or~106 at LC_X4_Y2_N7
--operation mode is normal

A1L57 = D0 & !D2 & (D3 $ !D1) # !D0 & D2 & (D3 $ !D1);


--A1L58 is reduce_or~107 at LC_X5_Y2_N5
--operation mode is normal

A1L58 = D2 # D0 & (D1 # !D3) # !D0 & (D1 $ D3);


--A1L47 is c~39 at LC_X4_Y2_N1
--operation mode is normal

A1L47 = D0 & (D2 & D3 & !D1 # !D2 & !D3 & D1);


--A1L59 is reduce_or~108 at LC_X5_Y2_N3
--operation mode is normal

A1L59 = D1 & D3 & (D2 $ D0) # !D1 & (D3 & !D2 & !D0 # !D3 & (D2 $ D0));


--A1L60 is reduce_or~109 at LC_X5_Y2_N6
--operation mode is normal

A1L60 = D0 & (D2 # D1 $ D3);


--A1L61 is reduce_or~110 at LC_X5_Y2_N0
--operation mode is normal

A1L61 = D1 & (D3 & D2 & !D0 # !D3 & !D2) # !D1 & (D3 & (D2 # !D0) # !D3 & D2 & !D0);


--A1L62 is reduce_or~111 at LC_X4_Y2_N2
--operation mode is normal

A1L62 = D2 & (D3 $ !D1) # !D2 & !D0 & D3 & !D1;


--buffer[0] is buffer[0] at LC_X2_Y2_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

buffer[0]_lut_out = GND;
buffer[0] = DFFEAS(buffer[0]_lut_out, GLOBAL(CLK), VCC, , , A1L10, , , VCC);


--buffer[1] is buffer[1] at LC_X2_Y2_N7
--operation mode is normal

buffer[1]_lut_out = A1L13;
buffer[1] = DFFEAS(buffer[1]_lut_out, GLOBAL(CLK), VCC, , , , , , );


--buffer[2] is buffer[2] at LC_X3_Y2_N9
--operation mode is normal

buffer[2]_lut_out = A1L16;
buffer[2] = DFFEAS(buffer[2]_lut_out, GLOBAL(CLK), VCC, , , , , , );


--buffer[3] is buffer[3] at LC_X2_Y2_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

buffer[3]_lut_out = GND;
buffer[3] = DFFEAS(buffer[3]_lut_out, GLOBAL(CLK), VCC, , , A1L19, , , VCC);


--buffer[4] is buffer[4] at LC_X4_Y2_N9
--operation mode is normal

buffer[4]_lut_out = A1L22;
buffer[4] = DFFEAS(buffer[4]_lut_out, GLOBAL(CLK), VCC, , , , , , );


--buffer[5] is buffer[5] at LC_X5_Y2_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

buffer[5]_lut_out = GND;
buffer[5] = DFFEAS(buffer[5]_lut_out, GLOBAL(CLK), VCC, , , A1L26, , , VCC);


--buffer[6] is buffer[6] at LC_X3_Y3_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

buffer[6]_lut_out = GND;
buffer[6] = DFFEAS(buffer[6]_lut_out, GLOBAL(CLK), VCC, , , A1L29, , , VCC);


--buffer[7] is buffer[7] at LC_X5_Y2_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

buffer[7]_lut_out = GND;
buffer[7] = DFFEAS(buffer[7]_lut_out, GLOBAL(CLK), VCC, , , A1L32, , , VCC);


--D3 is D3 at PIN_41
--operation mode is input

D3 = INPUT();


--D2 is D2 at PIN_40
--operation mode is input

D2 = INPUT();


--D1 is D1 at PIN_39
--operation mode is input

D1 = INPUT();


--D0 is D0 at PIN_38
--operation mode is input

D0 = INPUT();


--CLK is CLK at PIN_12
--operation mode is input

CLK = INPUT();


--a is a at PIN_2
--operation mode is output

a = OUTPUT(A1L34Q);


--b is b at PIN_1
--operation mode is output

b = OUTPUT(A1L45Q);


--c is c at PIN_7
--operation mode is output

c = OUTPUT(A1L48Q);


--d is d at PIN_6
--operation mode is output

d = OUTPUT(A1L50Q);


--e is e at PIN_5
--operation mode is output

e = OUTPUT(A1L52Q);


--f is f at PIN_3
--operation mode is output

f = OUTPUT(A1L54Q);


--g is g at PIN_4
--operation mode is output

g = OUTPUT(A1L56Q);


--CS1 is CS1 at PIN_100
--operation mode is output

CS1 = OUTPUT(A1L3Q);


--CS2 is CS2 at PIN_99
--operation mode is output

CS2 = OUTPUT(!A1L3Q);