?? seqdet2.tan.rpt
字號:
Timing Analyzer report for seqdet2
Sun Feb 22 16:39:13 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. tpd
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+------------+---------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------------+---------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 2.298 ns ; x ; state.C ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 6.781 ns ; state.H ; z ; clk ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 7.884 ns ; x ; z ; -- ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -1.593 ns ; x ; state.K ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.IDLE ; state.A ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+------------+---------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.IDLE ; state.A ; clk ; clk ; None ; None ; 1.116 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.L ; state.A ; clk ; clk ; None ; None ; 1.037 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.D ; state.A ; clk ; clk ; None ; None ; 0.968 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.K ; state.A ; clk ; clk ; None ; None ; 0.965 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.A ; state.B ; clk ; clk ; None ; None ; 0.938 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.B ; state.K ; clk ; clk ; None ; None ; 0.938 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.G ; state.H ; clk ; clk ; None ; None ; 0.875 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.G ; state.B ; clk ; clk ; None ; None ; 0.874 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.IDLE ; state.IDLE ; clk ; clk ; None ; None ; 0.868 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.K ; state.L ; clk ; clk ; None ; None ; 0.859 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.E ; state.A ; clk ; clk ; None ; None ; 0.856 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.J ; state.L ; clk ; clk ; None ; None ; 0.854 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.L ; state.IDLE ; clk ; clk ; None ; None ; 0.854 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.C ; state.C ; clk ; clk ; None ; None ; 0.847 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.A ; state.J ; clk ; clk ; None ; None ; 0.845 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.D ; state.E ; clk ; clk ; None ; None ; 0.844 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.J ; state.A ; clk ; clk ; None ; None ; 0.829 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.F ; state.IDLE ; clk ; clk ; None ; None ; 0.762 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.F ; state.G ; clk ; clk ; None ; None ; 0.761 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.B ; state.C ; clk ; clk ; None ; None ; 0.751 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.E ; state.F ; clk ; clk ; None ; None ; 0.717 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.H ; state.L ; clk ; clk ; None ; None ; 0.637 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.H ; state.I ; clk ; clk ; None ; None ; 0.636 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.I ; state.B ; clk ; clk ; None ; None ; 0.634 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.I ; state.J ; clk ; clk ; None ; None ; 0.631 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; state.C ; state.D ; clk ; clk ; None ; None ; 0.626 ns ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+------------+----------+
; N/A ; None ; 2.298 ns ; x ; state.C ; clk ;
; N/A ; None ; 2.292 ns ; x ; state.D ; clk ;
; N/A ; None ; 2.266 ns ; x ; state.L ; clk ;
; N/A ; None ; 2.264 ns ; x ; state.IDLE ; clk ;
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