; N/A   ; None         ; 2.262 ns   ; x    ; state.A    ; clk      ;
; N/A   ; None         ; 1.970 ns   ; x    ; state.F    ; clk      ;
; N/A   ; None         ; 1.968 ns   ; x    ; state.E    ; clk      ;
; N/A   ; None         ; 1.935 ns   ; x    ; state.I    ; clk      ;
; N/A   ; None         ; 1.934 ns   ; x    ; state.G    ; clk      ;
; N/A   ; None         ; 1.934 ns   ; x    ; state.J    ; clk      ;
; N/A   ; None         ; 1.929 ns   ; x    ; state.B    ; clk      ;
; N/A   ; None         ; 1.704 ns   ; x    ; state.H    ; clk      ;
; N/A   ; None         ; 1.703 ns   ; x    ; state.K    ; clk      ;
+-------+--------------+------------+------+------------+----------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+---------+----+------------+
; Slack ; Required tco ; Actual tco ; From    ; To ; From Clock ;
+-------+--------------+------------+---------+----+------------+
; N/A   ; None         ; 6.781 ns   ; state.H ; z  ; clk        ;
+-------+--------------+------------+---------+----+------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 7.884 ns        ; x    ; z  ;
+-------+-------------------+-----------------+------+----+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To         ; To Clock ;
+---------------+-------------+-----------+------+------------+----------+
; N/A           ; None        ; -1.593 ns ; x    ; state.K    ; clk      ;
; N/A           ; None        ; -1.594 ns ; x    ; state.H    ; clk      ;
; N/A           ; None        ; -1.819 ns ; x    ; state.B    ; clk      ;
; N/A           ; None        ; -1.824 ns ; x    ; state.G    ; clk      ;
; N/A           ; None        ; -1.824 ns ; x    ; state.J    ; clk      ;
; N/A           ; None        ; -1.825 ns ; x    ; state.I    ; clk      ;
; N/A           ; None        ; -1.858 ns ; x    ; state.E    ; clk      ;
; N/A           ; None        ; -1.860 ns ; x    ; state.F    ; clk      ;
; N/A           ; None        ; -2.152 ns ; x    ; state.A    ; clk      ;
; N/A           ; None        ; -2.154 ns ; x    ; state.IDLE ; clk      ;
; N/A           ; None        ; -2.156 ns ; x    ; state.L    ; clk      ;
; N/A           ; None        ; -2.182 ns ; x    ; state.D    ; clk      ;
; N/A           ; None        ; -2.188 ns ; x    ; state.C    ; clk      ;
+---------------+-------------+-----------+------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Feb 22 16:39:12 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seqdet2 -c seqdet2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "state.IDLE" and destination register "state.A"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.116 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N7; Fanout = 2; REG Node = 'state.IDLE'
            Info: 2: + IC(0.393 ns) + CELL(0.366 ns) = 0.759 ns; Loc. = LC_X1_Y1_N3; Fanout = 1; COMB Node = 'Selector4~40'
            Info: 3: + IC(0.134 ns) + CELL(0.223 ns) = 1.116 ns; Loc. = LC_X1_Y1_N4; Fanout = 2; REG Node = 'state.A'
            Info: Total cell delay = 0.589 ns ( 52.78 % )
            Info: Total interconnect delay = 0.527 ns ( 47.22 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.009 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 13; CLK Node = 'clk'
                Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N4; Fanout = 2; REG Node = 'state.A'
                Info: Total cell delay = 1.370 ns ( 45.53 % )
                Info: Total interconnect delay = 1.639 ns ( 54.47 % )
            Info: - Longest clock path from clock "clk" to source register is 3.009 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 13; CLK Node = 'clk'
                Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N7; Fanout = 2; REG Node = 'state.IDLE'
                Info: Total cell delay = 1.370 ns ( 45.53 % )
                Info: Total interconnect delay = 1.639 ns ( 54.47 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "state.C" (data pin = "x", clock pin = "clk") is 2.298 ns
    Info: + Longest pin to register delay is 5.297 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U20; Fanout = 14; PIN Node = 'x'
        Info: 2: + IC(3.524 ns) + CELL(0.539 ns) = 5.297 ns; Loc. = LC_X2_Y1_N6; Fanout = 2; REG Node = 'state.C'
        Info: Total cell delay = 1.773 ns ( 33.47 % )
        Info: Total interconnect delay = 3.524 ns ( 66.53 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.009 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 13; CLK Node = 'clk'
        Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X2_Y1_N6; Fanout = 2; REG Node = 'state.C'
        Info: Total cell delay = 1.370 ns ( 45.53 % )
        Info: Total interconnect delay = 1.639 ns ( 54.47 % )
Info: tco from clock "clk" to destination pin "z" through register "state.H" is 6.781 ns
    Info: + Longest clock path from clock "clk" to source register is 3.009 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 13; CLK Node = 'clk'
        Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N0; Fanout = 3; REG Node = 'state.H'
        Info: Total cell delay = 1.370 ns ( 45.53 % )
        Info: Total interconnect delay = 1.639 ns ( 54.47 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.616 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N0; Fanout = 3; REG Node = 'state.H'
        Info: 2: + IC(0.413 ns) + CELL(0.075 ns) = 0.488 ns; Loc. = LC_X1_Y1_N6; Fanout = 1; COMB Node = 'z~0'
        Info: 3: + IC(0.752 ns) + CELL(2.376 ns) = 3.616 ns; Loc. = PIN_U19; Fanout = 0; PIN Node = 'z'
        Info: Total cell delay = 2.451 ns ( 67.78 % )
        Info: Total interconnect delay = 1.165 ns ( 32.22 % )
Info: Longest tpd from source pin "x" to destination pin "z" is 7.884 ns
    Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U20; Fanout = 14; PIN Node = 'x'
    Info: 2: + IC(3.242 ns) + CELL(0.280 ns) = 4.756 ns; Loc. = LC_X1_Y1_N6; Fanout = 1; COMB Node = 'z~0'
    Info: 3: + IC(0.752 ns) + CELL(2.376 ns) = 7.884 ns; Loc. = PIN_U19; Fanout = 0; PIN Node = 'z'
    Info: Total cell delay = 3.890 ns ( 49.34 % )
    Info: Total interconnect delay = 3.994 ns ( 50.66 % )
Info: th for register "state.K" (data pin = "x", clock pin = "clk") is -1.593 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.009 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 13; CLK Node = 'clk'
        Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N1; Fanout = 2; REG Node = 'state.K'
        Info: Total cell delay = 1.370 ns ( 45.53 % )
        Info: Total interconnect delay = 1.639 ns ( 54.47 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.702 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U20; Fanout = 14; PIN Node = 'x'
        Info: 2: + IC(3.245 ns) + CELL(0.223 ns) = 4.702 ns; Loc. = LC_X1_Y1_N1; Fanout = 2; REG Node = 'state.K'
        Info: Total cell delay = 1.457 ns ( 30.99 % )
        Info: Total interconnect delay = 3.245 ns ( 69.01 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Feb 22 16:39:13 2009
    Info: Elapsed time: 00:00:02