?? ls138.tan.rpt
字號:
Classic Timing Analyzer report for ls138
Tue Feb 24 09:10:34 2009
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+-----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+-----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 14.402 ns ; G2BN ; Y6N ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+-----+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C12Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+-----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+-----+
; N/A ; None ; 14.402 ns ; G2BN ; Y6N ;
; N/A ; None ; 14.401 ns ; G2BN ; Y2N ;
; N/A ; None ; 14.400 ns ; G2BN ; Y4N ;
; N/A ; None ; 14.398 ns ; G2BN ; Y7N ;
; N/A ; None ; 14.397 ns ; G2BN ; Y3N ;
; N/A ; None ; 14.370 ns ; G2AN ; Y6N ;
; N/A ; None ; 14.369 ns ; G2AN ; Y2N ;
; N/A ; None ; 14.368 ns ; G2AN ; Y4N ;
; N/A ; None ; 14.366 ns ; G2AN ; Y7N ;
; N/A ; None ; 14.365 ns ; G2AN ; Y3N ;
; N/A ; None ; 14.059 ns ; G2BN ; Y5N ;
; N/A ; None ; 14.027 ns ; G2AN ; Y5N ;
; N/A ; None ; 13.955 ns ; G2BN ; Y0N ;
; N/A ; None ; 13.940 ns ; G2BN ; Y1N ;
; N/A ; None ; 13.923 ns ; G2AN ; Y0N ;
; N/A ; None ; 13.908 ns ; G2AN ; Y1N ;
; N/A ; None ; 12.874 ns ; G1 ; Y6N ;
; N/A ; None ; 12.873 ns ; G1 ; Y2N ;
; N/A ; None ; 12.872 ns ; G1 ; Y4N ;
; N/A ; None ; 12.870 ns ; G1 ; Y7N ;
; N/A ; None ; 12.869 ns ; G1 ; Y3N ;
; N/A ; None ; 12.700 ns ; C ; Y6N ;
; N/A ; None ; 12.699 ns ; C ; Y5N ;
; N/A ; None ; 12.690 ns ; C ; Y3N ;
; N/A ; None ; 12.687 ns ; C ; Y7N ;
; N/A ; None ; 12.686 ns ; C ; Y2N ;
; N/A ; None ; 12.677 ns ; C ; Y4N ;
; N/A ; None ; 12.531 ns ; G1 ; Y5N ;
; N/A ; None ; 12.427 ns ; G1 ; Y0N ;
; N/A ; None ; 12.412 ns ; G1 ; Y1N ;
; N/A ; None ; 12.247 ns ; C ; Y1N ;
; N/A ; None ; 12.236 ns ; C ; Y0N ;
; N/A ; None ; 11.746 ns ; B ; Y6N ;
; N/A ; None ; 11.744 ns ; B ; Y2N ;
; N/A ; None ; 11.743 ns ; B ; Y4N ;
; N/A ; None ; 11.741 ns ; B ; Y5N ;
; N/A ; None ; 11.741 ns ; B ; Y7N ;
; N/A ; None ; 11.740 ns ; B ; Y3N ;
; N/A ; None ; 11.611 ns ; A ; Y6N ;
; N/A ; None ; 11.610 ns ; A ; Y5N ;
; N/A ; None ; 11.602 ns ; A ; Y3N ;
; N/A ; None ; 11.599 ns ; A ; Y7N ;
; N/A ; None ; 11.596 ns ; A ; Y2N ;
; N/A ; None ; 11.592 ns ; A ; Y4N ;
; N/A ; None ; 11.298 ns ; B ; Y0N ;
; N/A ; None ; 11.280 ns ; B ; Y1N ;
; N/A ; None ; 11.158 ns ; A ; Y1N ;
; N/A ; None ; 11.146 ns ; A ; Y0N ;
+-------+-------------------+-----------------+------+-----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
Info: Processing started: Tue Feb 24 09:10:33 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ls138 -c ls138 --timing_analysis_only
Info: Longest tpd from source pin "G2BN" to destination pin "Y6N" is 14.402 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_84; Fanout = 1; PIN Node = 'G2BN'
Info: 2: + IC(8.512 ns) + CELL(0.114 ns) = 10.101 ns; Loc. = LC_X52_Y4_N6; Fanout = 8; COMB Node = '1~13'
Info: 3: + IC(0.523 ns) + CELL(0.114 ns) = 10.738 ns; Loc. = LC_X52_Y4_N8; Fanout = 1; COMB Node = '21'
Info: 4: + IC(1.540 ns) + CELL(2.124 ns) = 14.402 ns; Loc. = PIN_138; Fanout = 0; PIN Node = 'Y6N'
Info: Total cell delay = 3.827 ns ( 26.57 % )
Info: Total interconnect delay = 10.575 ns ( 73.43 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 113 megabytes of memory during processing
Info: Processing ended: Tue Feb 24 09:10:34 2009
Info: Elapsed time: 00:00:01
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