?? sdram.v
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/****************************************************************************************** File Name: MT48LC16M8A2.V * Version: 1.0a* Date: August 4th, 2000* Model: BUS Functional* Simulator: Model Technology** Dependencies: None** Author: Son P. Huynh* Email: sphuynh@micron.com* Phone: (208) 368-3825* Company: Micron Technology, Inc.* Model: MT48LC16M8A2 (4Meg x 8 x 4 Banks)** Description: Micron 128Mb SDRAM Verilog model** Limitation: - Doesn't check for 4096 cycle refresh** Note: - Set simulator resolution to "ps" timescale* - Set Debug = 0 to disable $display messages** Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY * WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.** Copyright
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