LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT05S IS
  PORT(CLK,EN05M,EN05B:IN STD_LOGIC;
       DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY CNT05S;

ARCHITECTURE ART OF CNT05S IS
  SIGNAL CNT3B:STD_LOGIC_VECTOR(2 DOWNTO 0);
  BEGIN 
  PROCESS(CLK,EN05M,EN05B) IS
    BEGIN
    IF(CLK'EVENT AND CLK='1') THEN
      IF EN05M='1' THEN CNT3B<=CNT3B+1;
      ELSIF EN05B='1' THEN CNT3B<=CNT3B+1;
      ELSIF EN05B='0' THEN CNT3B<=CNT3B-CNT3B-1;
      END IF;
    END IF;
  END PROCESS;
  PROCESS(CNT3B) IS
  BEGIN
  CASE CNT3B IS
  WHEN"000"=>DOUT5<="00000101";
  WHEN"001"=>DOUT5<="00000100";
  WHEN"010"=>DOUT5<="00000011";
  WHEN"011"=>DOUT5<="00000010";
  WHEN"100"=>DOUT5<="00000001";
  WHEN OTHERS=>DOUT5<="00000000";
  END CASE;
 END PROCESS;
END ARCHITECTURE ART;