?? phasea.rpt
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Project Information f:\dds2\dds\phasea.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/21/2006 09:59:49
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
PHASEA
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
phasea EPF10K10LC84-3 34 10 0 0 0 % 68 11 %
User Pins: 34 10 0
Project Information f:\dds2\dds\phasea.rpt
** FILE HIERARCHY **
|lpm_add_sub:lpm_add_1|
|lpm_add_sub:lpm_add_1|addcore:adder|
|lpm_add_sub:lpm_add_1|altshift:result_ext_latency_ffs|
|lpm_add_sub:lpm_add_1|altshift:carry_ext_latency_ffs|
|lpm_add_sub:lpm_add_1|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:lpm_add_2|
|lpm_add_sub:lpm_add_2|addcore:adder|
|lpm_add_sub:lpm_add_2|altshift:result_ext_latency_ffs|
|lpm_add_sub:lpm_add_2|altshift:carry_ext_latency_ffs|
|lpm_add_sub:lpm_add_2|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:lpm_add_3|
|lpm_add_sub:lpm_add_3|addcore:adder|
|lpm_add_sub:lpm_add_3|altshift:result_ext_latency_ffs|
|lpm_add_sub:lpm_add_3|altshift:carry_ext_latency_ffs|
|lpm_add_sub:lpm_add_3|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:lpm_add_4|
|lpm_add_sub:lpm_add_4|addcore:adder|
|lpm_add_sub:lpm_add_4|altshift:result_ext_latency_ffs|
|lpm_add_sub:lpm_add_4|altshift:carry_ext_latency_ffs|
|lpm_add_sub:lpm_add_4|altshift:oflow_ext_latency_ffs|
Device-Specific Information: f:\dds2\dds\phasea.rpt
phasea
***** Logic for device 'phasea' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
S S ^
Y S S Y S S C
N R Y Y N Y Y R R R R R O
C E N N C N N E E E E E N
F S P C C F P V C R S C S G S S S S F
R E H F F R H C F E Y F E N E E E E _ ^
E R A R R E A C R S S R R D R R R R # D n
Q V S E E Q S I E E C E V I V V V V T O C
1 E E Q Q 2 E N Q T L Q E N E E E E C N E
1 D 3 7 8 1 5 T 3 N K 0 D T D D D D K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | SYNCFREQ14
^nCE | 14 72 | SYNCFREQ20
#TDI | 15 71 | SYNCFREQ18
PHASE4 | 16 70 | SYNCFREQ13
SYNCFREQ19 | 17 69 | SYNCFREQ16
SYNCFREQ15 | 18 68 | GNDINT
SYNCFREQ12 | 19 67 | SYNCFREQ9
VCCINT | 20 66 | SYNCFREQ6
COS | 21 65 | SYNCFREQ5
SYNCFREQ10 | 22 EPF10K10LC84-3 64 | SYNCFREQ30
PHASE6 | 23 63 | VCCINT
PHASE7 | 24 62 | SYNCFREQ23
SIN | 25 61 | SYNCFREQ26
GNDINT | 26 60 | SYNCFREQ25
PHASE2 | 27 59 | SYNCFREQ22
PHASE0 | 28 58 | SYNCFREQ24
PHASE1 | 29 57 | #TMS
SYNCFREQ27 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R S S S S V G S S S V G R R R R R R R
C n E Y Y Y Y C N Y Y Y C N E E E E E E E
C C S N N N N C D N N N C D S S S S S S S
I O E C C C C I I C C C I I E E E E E E E
N N R F F F F N N F F F N N R R R R R R R
T F V R R R R T T R R R T T V V V V V V V
I E E E E E E E E E E E E E E E
G D Q Q Q Q Q Q Q D D D D D D D
1 3 2 2 4 2 1
7 1 9 8
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\dds2\dds\phasea.rpt
phasea
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A6 6/ 8( 75%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
A9 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
A12 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
B1 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
B4 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
B6 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
B7 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
C1 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
C8 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 38/53 ( 71%)
Total logic cells used: 68/576 ( 11%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.41/4 ( 85%)
Total fan-in: 232/2304 ( 10%)
Total input pins required: 34
Total input I/O cell registers required: 0
Total output pins required: 10
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 68
Total flipflops required: 36
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 1/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 6 0 0 7 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 21/0
B: 8 0 0 8 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32/0
C: 8 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15/0
Total: 16 0 0 8 0 14 8 7 7 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 68/0
Device-Specific Information: f:\dds2\dds\phasea.rpt
phasea
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
2 - - - -- INPUT 0 0 0 36 RESETN
84 - - - -- INPUT 0 0 0 3 SYNCFREQ0
44 - - - -- INPUT 0 0 0 2 SYNCFREQ1
43 - - - -- INPUT 0 0 0 2 SYNCFREQ2
3 - - - 12 INPUT 0 0 0 2 SYNCFREQ3
42 - - - -- INPUT 0 0 0 2 SYNCFREQ4
65 - - B -- INPUT 0 0 0 2 SYNCFREQ5
66 - - B -- INPUT 0 0 0 2 SYNCFREQ6
8 - - - 03 INPUT 0 0 0 2 SYNCFREQ7
7 - - - 03 INPUT 0 0 0 2 SYNCFREQ8
67 - - B -- INPUT 0 0 0 2 SYNCFREQ9
22 - - B -- INPUT 0 0 0 2 SYNCFREQ10
11 - - - 01 INPUT 0 0 0 2 SYNCFREQ11
19 - - A -- INPUT 0 0 0 2 SYNCFREQ12
70 - - A -- INPUT 0 0 0 2 SYNCFREQ13
73 - - A -- INPUT 0 0 0 2 SYNCFREQ14
18 - - A -- INPUT 0 0 0 2 SYNCFREQ15
69 - - A -- INPUT 0 0 0 2 SYNCFREQ16
36 - - - 07 INPUT 0 0 0 2 SYNCFREQ17
71 - - A -- INPUT 0 0 0 2 SYNCFREQ18
17 - - A -- INPUT 0 0 0 2 SYNCFREQ19
72 - - A -- INPUT 0 0 0 2 SYNCFREQ20
6 - - - 04 INPUT 0 0 0 2 SYNCFREQ21
59 - - C -- INPUT 0 0 0 2 SYNCFREQ22
62 - - C -- INPUT 0 0 0 2 SYNCFREQ23
58 - - C -- INPUT 0 0 0 2 SYNCFREQ24
60 - - C -- INPUT 0 0 0 2 SYNCFREQ25
61 - - C -- INPUT 0 0 0 2 SYNCFREQ26
30 - - C -- INPUT 0 0 0 2 SYNCFREQ27
39 - - - 11 INPUT 0 0 0 2 SYNCFREQ28
38 - - - 10 INPUT 0 0 0 2 SYNCFREQ29
64 - - B -- INPUT 0 0 0 2 SYNCFREQ30
37 - - - 09 INPUT 0 0 0 2 SYNCFREQ31
1 - - - -- INPUT G 0 0 0 0 SYSCLK
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\dds2\dds\phasea.rpt
phasea
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