?? nco.vwf

?? 利用FPGA實現的DDS
?? VWF
?? 第 1 頁 / 共 4 頁
字號:
			LEVEL 0 FOR 639.929;
			LEVEL 1 FOR 640.0;
			LEVEL 0 FOR 0.071;
			LEVEL 1 FOR 639.929;
		}
		LEVEL 0 FOR 640.0;
		LEVEL 1 FOR 0.071;
		LEVEL 0 FOR 639.929;
		LEVEL 1 FOR 318.91;
	}
}

TRANSITION_LIST("MSIN")
{
	NODE
	{
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		NODE
		{
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			LEVEL 0 FOR 1280.0;
			LEVEL 1 FOR 1280.0;
		}
		LEVEL 0 FOR 1280.0;
		LEVEL 1 FOR 1280.0;
		LEVEL 0 FOR 959.361;
	}
}

TRANSITION_LIST("NCOOUT[7]")
{
	NODE
	{
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		NODE
		{
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		}
		LEVEL 1 FOR 1280.0;
		LEVEL 0 FOR 1280.0;
		LEVEL 1 FOR 919.541;
	}
}

TRANSITION_LIST("NCOOUT[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 340.758;
		NODE
		{
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		LEVEL 1 FOR 210.0;
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	}
}

TRANSITION_LIST("NCOOUT[5]")
{
	NODE
	{
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}

TRANSITION_LIST("NCOOUT[4]")
{
	NODE
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}

TRANSITION_LIST("NCOOUT[3]")
{
	NODE
	{
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}

TRANSITION_LIST("NCOOUT[2]")
{
	NODE
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		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		NODE
		{
			REPEAT = 5;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 20.0;
		}
		NODE
		{
			REPEAT = 3;
			LEVEL 0 FOR 20.0;
			LEVEL 1 FOR 20.0;
		}
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 160.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 30.0;
		NODE
		{
			REPEAT = 3;
			LEVEL 1 FOR 20.0;
			LEVEL 0 FOR 20.0;
		}
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 20.0;
			LEVEL 0 FOR 10.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 20.0;
			LEVEL 0 FOR 10.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 20.0;
		}
		LEVEL 1 FOR 10.0;
		NODE
		{
			REPEAT = 3;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 20.0;
		}
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 20.0;
			LEVEL 1 FOR 20.0;
		}
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 180.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 30.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 30.0;
			LEVEL 1 FOR 20.0;
		}
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		NODE
		{
			REPEAT = 3;
?? 文件大小 459 K
?? 上傳用戶 simoncxl
?? 所屬分類 VHDL/FPGA/Verilog
??? 相關標簽

#FPGA #DDS
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