?? phasea.pin
字號:
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
----------------------------------------------------------------------------
CHIP "phasea" ASSIGNED TO AN EPF10K10LC84-3
SYSCLK : 1
RESETN : 2
SYNCFREQ3 : 3
VCCINT : 4
PHASE5 : 5
SYNCFREQ21 : 6
SYNCFREQ8 : 7
SYNCFREQ7 : 8
PHASE3 : 9
RESERVED : 10
SYNCFREQ11 : 11
DATA0 : 12
DCLK : 13
nCE : 14
TDI : 15
PHASE4 : 16
SYNCFREQ19 : 17
SYNCFREQ15 : 18
SYNCFREQ12 : 19
VCCINT : 20
COS : 21
SYNCFREQ10 : 22
PHASE6 : 23
PHASE7 : 24
SIN : 25
GNDINT : 26
PHASE2 : 27
PHASE0 : 28
PHASE1 : 29
SYNCFREQ27 : 30
MSEL0 : 31
MSEL1 : 32
VCCINT : 33
nCONFIG : 34
RESERVED : 35
SYNCFREQ17 : 36
SYNCFREQ31 : 37
SYNCFREQ29 : 38
SYNCFREQ28 : 39
VCCINT : 40
GNDINT : 41
SYNCFREQ4 : 42
SYNCFREQ2 : 43
SYNCFREQ1 : 44
VCCINT : 45
GNDINT : 46
RESERVED : 47
RESERVED : 48
RESERVED : 49
RESERVED : 50
RESERVED : 51
RESERVED : 52
RESERVED : 53
RESERVED : 54
nSTATUS : 55
TRST : 56
TMS : 57
SYNCFREQ24 : 58
SYNCFREQ22 : 59
SYNCFREQ25 : 60
SYNCFREQ26 : 61
SYNCFREQ23 : 62
VCCINT : 63
SYNCFREQ30 : 64
SYNCFREQ5 : 65
SYNCFREQ6 : 66
SYNCFREQ9 : 67
GNDINT : 68
SYNCFREQ16 : 69
SYNCFREQ13 : 70
SYNCFREQ18 : 71
SYNCFREQ20 : 72
SYNCFREQ14 : 73
TDO : 74
nCEO : 75
CONF_DONE : 76
TCK : 77
RESERVED : 78
RESERVED : 79
RESERVED : 80
RESERVED : 81
GNDINT : 82
RESERVED : 83
SYNCFREQ0 : 84
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