+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Jun 04 12:50:59 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lift -c lift --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "buttonclk" is an undefined clock
    Info: Assuming node "liftclk" is an undefined clock
Info: Clock "buttonclk" Internal fmax is restricted to 420.17 MHz between source register "fuplight[5]~reg0" and destination register "fuplight[5]~reg0"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.961 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y21_N27; Fanout = 5; REG Node = 'fuplight[5]~reg0'
            Info: 2: + IC(0.324 ns) + CELL(0.150 ns) = 0.474 ns; Loc. = LCCOMB_X63_Y21_N2; Fanout = 1; COMB Node = 'fuplight~904'
            Info: 3: + IC(0.254 ns) + CELL(0.149 ns) = 0.877 ns; Loc. = LCCOMB_X63_Y21_N26; Fanout = 1; COMB Node = 'fuplight~905'
            Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 0.961 ns; Loc. = LCFF_X63_Y21_N27; Fanout = 5; REG Node = 'fuplight[5]~reg0'
            Info: Total cell delay = 0.383 ns ( 39.85 % )
            Info: Total interconnect delay = 0.578 ns ( 60.15 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "buttonclk" to destination register is 2.680 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 1; CLK Node = 'buttonclk'
                Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G3; Fanout = 21; COMB Node = 'buttonclk~clkctrl'
                Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X63_Y21_N27; Fanout = 5; REG Node = 'fuplight[5]~reg0'
                Info: Total cell delay = 1.536 ns ( 57.31 % )
                Info: Total interconnect delay = 1.144 ns ( 42.69 % )
            Info: - Longest clock path from clock "buttonclk" to source register is 2.680 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 1; CLK Node = 'buttonclk'
                Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G3; Fanout = 21; COMB Node = 'buttonclk~clkctrl'
                Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X63_Y21_N27; Fanout = 5; REG Node = 'fuplight[5]~reg0'
                Info: Total cell delay = 1.536 ns ( 57.31 % )
                Info: Total interconnect delay = 1.144 ns ( 42.69 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: Clock "liftclk" has Internal fmax of 225.17 MHz between source register "\ctrlift:pos[0]" and destination register "mylift.doorclose" (period= 4.441 ns)
    Info: + Longest register to register delay is 4.227 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X60_Y21_N17; Fanout = 43; REG Node = '\ctrlift:pos[0]'
        Info: 2: + IC(0.564 ns) + CELL(0.438 ns) = 1.002 ns; Loc. = LCCOMB_X59_Y21_N4; Fanout = 2; COMB Node = 'Mux1~125'
        Info: 3: + IC(0.698 ns) + CELL(0.438 ns) = 2.138 ns; Loc. = LCCOMB_X60_Y21_N12; Fanout = 1; COMB Node = 'Mux4~22'
        Info: 4: + IC(0.247 ns) + CELL(0.150 ns) = 2.535 ns; Loc. = LCCOMB_X60_Y21_N30; Fanout = 1; COMB Node = 'Mux4~23'
        Info: 5: + IC(0.247 ns) + CELL(0.150 ns) = 2.932 ns; Loc. = LCCOMB_X60_Y21_N10; Fanout = 1; COMB Node = 'mylift~3191'
        Info: 6: + IC(0.248 ns) + CELL(0.149 ns) = 3.329 ns; Loc. = LCCOMB_X60_Y21_N28; Fanout = 2; COMB Node = 'mylift~3194'
        Info: 7: + IC(0.256 ns) + CELL(0.150 ns) = 3.735 ns; Loc. = LCCOMB_X60_Y21_N0; Fanout = 1; COMB Node = 'Selector8~286'
        Info: 8: + IC(0.259 ns) + CELL(0.149 ns) = 4.143 ns; Loc. = LCCOMB_X60_Y21_N24; Fanout = 1; COMB Node = 'Selector8~287'
        Info: 9: + IC(0.000 ns) + CELL(0.084 ns) = 4.227 ns; Loc. = LCFF_X60_Y21_N25; Fanout = 6; REG Node = 'mylift.doorclose'
        Info: Total cell delay = 1.708 ns ( 40.41 % )
        Info: Total interconnect delay = 2.519 ns ( 59.59 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "liftclk" to destination register is 2.650 ns
            Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; CLK Node = 'liftclk'
            Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.092 ns; Loc. = CLKCTRL_G11; Fanout = 17; COMB Node = 'liftclk~clkctrl'
            Info: 3: + IC(1.021 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X60_Y21_N25; Fanout = 6; REG Node = 'mylift.doorclose'
            Info: Total cell delay = 1.516 ns ( 57.21 % )
            Info: Total interconnect delay = 1.134 ns ( 42.79 % )
        Info: - Longest clock path from clock "liftclk" to source register is 2.650 ns
            Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; CLK Node = 'liftclk'
            Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.092 ns; Loc. = CLKCTRL_G11; Fanout = 17; COMB Node = 'liftclk~clkctrl'
            Info: 3: + IC(1.021 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X60_Y21_N17; Fanout = 43; REG Node = '\ctrlift:pos[0]'
            Info: Total cell delay = 1.516 ns ( 57.21 % )
            Info: Total interconnect delay = 1.134 ns ( 42.79 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "stoplight[6]~reg0" (data pin = "stop2button", clock pin = "buttonclk") is 6.313 ns
    Info: + Longest pin to register delay is 9.030 ns
        Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_T7; Fanout = 3; PIN Node = 'stop2button'
        Info: 2: + IC(6.621 ns) + CELL(0.275 ns) = 7.728 ns; Loc. = LCCOMB_X61_Y20_N24; Fanout = 3; COMB Node = 'stoplight~892'
        Info: 3: + IC(0.671 ns) + CELL(0.150 ns) = 8.549 ns; Loc. = LCCOMB_X59_Y20_N30; Fanout = 1; COMB Node = 'stoplight~896'
        Info: 4: + IC(0.248 ns) + CELL(0.149 ns) = 8.946 ns; Loc. = LCCOMB_X59_Y20_N20; Fanout = 1; COMB Node = 'stoplight~897'
        Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 9.030 ns; Loc. = LCFF_X59_Y20_N21; Fanout = 6; REG Node = 'stoplight[6]~reg0'
        Info: Total cell delay = 1.490 ns ( 16.50 % )
        Info: Total interconnect delay = 7.540 ns ( 83.50 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "buttonclk" to destination register is 2.681 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 1; CLK Node = 'buttonclk'
        Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G3; Fanout = 21; COMB Node = 'buttonclk~clkctrl'
        Info: 3: + IC(1.032 ns) + CELL(0.537 ns) = 2.681 ns; Loc. = LCFF_X59_Y20_N21; Fanout = 6; REG Node = 'stoplight[6]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.29 % )
        Info: Total interconnect delay = 1.145 ns ( 42.71 % )
Info: tco from clock "buttonclk" to destination pin "lightout[4]" through register "display:u2|dp[4]" is 10.067 ns
    Info: + Longest clock path from clock "buttonclk" to source register is 2.679 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 1; CLK Node = 'buttonclk'
        Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G3; Fanout = 21; COMB Node = 'buttonclk~clkctrl'
        Info: 3: + IC(1.030 ns) + CELL(0.537 ns) = 2.679 ns; Loc. = LCFF_X62_Y21_N11; Fanout = 1; REG Node = 'display:u2|dp[4]'
        Info: Total cell delay = 1.536 ns ( 57.33 % )
        Info: Total interconnect delay = 1.143 ns ( 42.67 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 7.138 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X62_Y21_N11; Fanout = 1; REG Node = 'display:u2|dp[4]'
        Info: 2: + IC(4.340 ns) + CELL(2.798 ns) = 7.138 ns; Loc. = PIN_AE11; Fanout = 0; PIN Node = 'lightout[4]'
        Info: Total cell delay = 2.798 ns ( 39.20 % )
        Info: Total interconnect delay = 4.340 ns ( 60.80 % )
Info: th for register "fuplight[1]~reg0" (data pin = "f1upbutton", clock pin = "buttonclk") is 0.813 ns
    Info: + Longest clock path from clock "buttonclk" to destination register is 2.680 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 1; CLK Node = 'buttonclk'
        Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G3; Fanout = 21; COMB Node = 'buttonclk~clkctrl'
        Info: 3: + IC(1.031 ns) + CELL(0.537 ns) = 2.680 ns; Loc. = LCFF_X63_Y21_N31; Fanout = 7; REG Node = 'fuplight[1]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.31 % )
        Info: Total interconnect delay = 1.144 ns ( 42.69 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.133 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N25; Fanout = 4; PIN Node = 'f1upbutton'
        Info: 2: + IC(0.900 ns) + CELL(0.150 ns) = 2.049 ns; Loc. = LCCOMB_X63_Y21_N30; Fanout = 1; COMB Node = 'fuplight[1]~896'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.133 ns; Loc. = LCFF_X63_Y21_N31; Fanout = 7; REG Node = 'fuplight[1]~reg0'
        Info: Total cell delay = 1.233 ns ( 57.81 % )
        Info: Total interconnect delay = 0.900 ns ( 42.19 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 112 megabytes of memory during processing
    Info: Processing ended: Wed Jun 04 12:50:59 2008
    Info: Elapsed time: 00:00:00