LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fenpin IS
  PORT(clk: IN STD_LOGIC;
       clk1m,clk10,clk1: OUT STD_LOGIC);
END ENTITY fenpin ;

ARCHITECTURE behave OF  fenpin IS
	signal cl1,cl2,cl3:std_logic;
begin
	process(clk)
		variable con1:integer range 1 to 25;
	begin
		if (clk'event and clk='1')then
			if con1=25 then
				cl1<=not cl1;
				con1:=1;
			else
				con1:=con1 + 1;
			end if;
		end if;
	end process;
	
	process(cl1)
		variable con2:integer range 1 to 50000;
	begin
		if (cl1'event and cl1='1') then
			if con2=50000 then
				cl2<=not cl2;
				con2:=1;
			else
				con2:=con2 + 1;
			end if;
		end if;
	end process;
	
	process(cl2)
		variable con3:integer range 1 to 5;
	begin
		if (cl2'event and cl2='1') then
			if con3=5 then
				cl3<=not cl3;
				con3:=1;
			else
				con3:=con3 + 1;
			end if;
		end if;
	end process;
	
	clk1m<=cl1;
	clk10<=cl2;
	clk1<=cl3;
	
END ARCHITECTURE behave;