// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 - 2008 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code for use
// in synthesis for any Lattice programmable logic product. Other
// use of this code, including the selling or duplication of any
// portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Lattice Semiconductor provides no warranty
// regarding the use or functionality of this code.
//
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//
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// Code Revision History :
// --------------------------------------------------------------------
// Ver: | Author |Mod. Date |Changes Made:
// V1.0 |        |          | Initial ver
// V1.1 | S.R.   |18/12/08  | modified to support Mico8
// --------------------------------------------------------------------

`ifndef RXCVER_FILE
`define RXCVER_FILE
`include "system_conf.v"
`include "rxcver_fifo.v"
`timescale 1ns/10ps
module rxcver #(parameter DATAWIDTH=8,
                parameter FIFO=0)
     (
     // Global reset and clock
     reset,
     clk,
     // Register
     rbr,
     rbr_fifo,	     
     // Rising edge of rbr, lsr read strobes
     rbr_rd,
     lsr_rd,
     // Receiver input
     sin,
     // Receiver control
     databits,
     parity_en,
     parity_even,
     parity_stick,
     // Receiver status
     rx_rdy,
     overrun_err,
     parity_err,
     frame_err,
     break_int,
     fifo_empty,
     fifo_almost_full,
     divisor  
     );
   
   input         reset   ;
   input         clk     ;
   input         rbr_rd ;
   input         lsr_rd ;
   input         sin    ;
   input [1:0]   databits ;
   input         parity_en;
   input         parity_even;
   input         parity_stick;

   output [7:0]           rbr_fifo;
   output [DATAWIDTH-1:0]  rbr ;  
   output 		   rx_rdy      ;
   output 		   overrun_err ;
   output 		   parity_err  ;
   output 		   frame_err   ;
   output 		   break_int   ;
   output                  fifo_empty  ;
   output                  fifo_almost_full;
   input[15:0]             divisor;
   
   reg [3:0] 	           databit_recved_num;
   reg [DATAWIDTH-1:0]     rsr;
   reg 			   rx_parity_err  ;
   reg 			   rx_frame_err ;
   reg 			   rx_idle;
   reg 			   rbr_datardy;
   reg [3:0] 	           count;
   reg 			   hunt;
   reg 			   hunt_one;
   reg 			   sin_d0;
   reg 			   sin_d1;
   reg 			   rx_frame_err_d1;
   reg 			   rx_idle_d1;
   reg 			   overrun_err_int;
   reg 			   parity_err_int;
   reg 			   frame_err_int;
   reg 			   break_int_int;
   reg 			   sampled_once;
   reg 			   rxclk_en;    

   wire [7:0]             rbr_fifo;
   wire [2:0]             rbr_fifo_error;

   reg [DATAWIDTH-1:0]     rbr; 

   
   // State Machine Definition
   parameter 	idle   = 3'b000;
   parameter 	shift  = 3'b001;
   parameter 	parity = 3'b010;
   parameter 	stop   = 3'b011;
   parameter    idle1  = 3'b100;
   reg [2:0]    cs_state;
parameter    lat_family = `LATTICE_FAMILY;
   // FIFO signals for FIFO mode
   wire         fifo_full;
   wire         fifo_empty;
   wire         fifo_almost_full;
   wire         fifo_almost_empty;
   reg[10:0]    fifo_din;
   reg          fifo_wr;
   reg          fifo_wr_q;
   wire         fifo_wr_pulse;

   reg [15:0]   counter;
   wire [15:0]  divisor_2;
   assign divisor_2 = divisor/2;
   reg          sin_d0_delay; 

   
   ////////////////////////////////////////////////////////////////////////////////
   // Generate hunt
   ////////////////////////////////////////////////////////////////////////////////
   
   // hunt : will be TRUE when start bit is found
     always @(posedge clk or posedge reset) begin
     if (reset)
       hunt <= 1'b0;
     else if ((cs_state == idle) && (sin_d0 == 1'b0) && (sin_d1 == 1'b1))
       // Set Hunt when SIN falling edge is found at the idle state
       hunt <= 1'b1;
     else if (sampled_once && ~sin_d0)
        // Start bit is successfully sampled twice after framing error
        // set Hunt_r "true" for resynchronizing of next frame
       hunt <= 1'b1;
     else if (~rx_idle || sin_d0)
       hunt <= 1'b0;
     end
   
   
   // hunt_one :
   //   hunt_one, used for BI flag generation, indicates that there is at
   //   least a '1' in the (data + parity + stop) bits of the frame.
   //   Break Interrupt flag(BI) is set to '1' whenever the received input
   //   is held at the '0' state for all bits in the frame (Start bit +
   //   Data bits + Parity bit + Stop bit).  So, as long as hunt_one is still
   //   low after all bits are received, BI will be set to '1'.
     always @(posedge clk or posedge reset) begin
        if (reset)
          hunt_one <= 1'b0;
        else if (hunt)
          hunt_one <= 1'b0;
        else if ((rx_idle == 1'b0) && (counter == divisor_2) && (sin_d0 == 1'b1))
          hunt_one <= 1'b1;
     end
   
   // rbr_datardy :
   // This will be set to indicate that the data in rbr is ready for read and
   // will be cleared after rbr is read.
   //
   generate 
   begin
      if (FIFO == 1) begin
       always @(posedge clk or posedge reset) begin
        if (reset) 
          rbr_datardy <= 1'b0;
        else begin
	   if (fifo_empty)	   
            // clear RbrDataRDY when RBR is read by CPU in 450 or FIFO is
	    // empty in 550 mode
            rbr_datardy <= 1'b0; 
	   else if (!fifo_empty)	   
            // set RbrDataRDY at RxIdle_r rising edge
            rbr_datardy <= 1'b1;
        end    
       end
      end
      else begin
       always @(posedge clk or posedge reset) begin
        if (reset) 
          rbr_datardy <= 1'b0;
        else begin
           if (rbr_rd)   	   
            // clear RbrDataRDY when RBR is read by CPU in 450 or FIFO is
	    // empty in 550 mode
            rbr_datardy <= 1'b0;
           else if ((rx_idle == 1'b1) && (rx_idle_d1 == 1'b0))	   
            // set RbrDataRDY at RxIdle_r rising edge
            rbr_datardy <= 1'b1;
        end    
       end
      end
   end
endgenerate
   
   // sampled_once :
   //   This will be set for one clk clock after a framing error occurs not
   //   because of BREAK and a low sin signal is sampled by the clk right
   //   after the sample time of the Stop bit which causes the framing error.
   always @ (posedge clk or posedge reset)  begin 
        if (reset)
          sampled_once <= 1'b0;
        else if (rx_frame_err && ~rx_frame_err_d1 && ~sin_d0 && hunt_one)
          // Start bit got sampled once
          sampled_once <= 1'b1;
        else
          sampled_once <= 1'b0;
     end
   
   
   // rx_idle Flag
     always @ (posedge clk or posedge reset)  begin
     if (reset)
          rx_idle <= 1'b1;                               
     else if (cs_state == idle)
          rx_idle <= 1'b1;
     else
          rx_idle <= 1'b0;		
     end
   
    ////////////////////////////////////////////////////////////////////////////////
   // Receiver Finite State Machine
   ////////////////////////////////////////////////////////////////////////////////
   //  rx_parity_err:
   //               rx_parity_err is a dynamic Parity Error indicator which is
   //               initialized to 0 for even parity and 1 for odd parity.
   //               For odd parity, if there are odd number of '1's in the
   //               (data + parity) bits, the XOR will bring rx_parity_err back to 0
   //               which means no parity error, otherwise rx_parity_err will be 1 to
   //               indicate a parity error.
   // parity_stick='1' means Stick Parity is enabled.  In this case,
   //               the accumulated dynamic rx_parity_err result will be ignored.  A new
   //               value will be assigned to rx_parity_err based on the even/odd parity
   //               mode setting and the sin sampled in parity bit.
   //                  parity_even='0'(odd parity):
   //                     sin needs to be '1', otherwise it's a stick parity error.
   //                  parity_even='1'(even parity):
   //                     sin needs to be '0', otherwise it's a stick parity error.
   
   always @ (posedge clk or posedge reset) begin 
        if (reset) begin
           rsr <= 0;
           databit_recved_num <= 4'h0;
           rx_parity_err <= 1'b1;