?? _primary.vhd
字號:
library verilog;use verilog.vl_types.all;entity uart_ctrl is generic( WRITE_STEP1 : integer := 0; WRITE_STEP2 : integer := 1; WRITE_STEP3 : integer := 2; WRITE_STEP4 : integer := 3; WRITE_STEP5 : integer := 4; RECEIVE_STEP1 : integer := 0; RECEIVE_STEP2 : integer := 1; RECEIVE_STEP3 : integer := 2; RECEIVE_STEP4 : integer := 3 ); port( CLK : in vl_logic; RST : in vl_logic; DATA_TRF : out vl_logic_vector(7 downto 0); DATA_RCE : out vl_logic_vector(7 downto 0); RE : out vl_logic; WE : out vl_logic; CS : out vl_logic; TX : out vl_logic; RX : in vl_logic );end uart_ctrl;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -