?? _primary.vhd
字號:
library verilog;use verilog.vl_types.all;entity Rx_async is generic( RX_FIFO : integer := 0; CUARTO01 : integer := 0; CUARTI01 : integer := 1; CUARTl01 : integer := 2 ); port( clk : in vl_logic; baud_clock : in vl_logic; reset_n : in vl_logic; bit8 : in vl_logic; parity_en : in vl_logic; odd_n_even : in vl_logic; read_rx_byte : in vl_logic; clear_parity : in vl_logic; rx : in vl_logic; overflow : out vl_logic; parity_err : out vl_logic; clear_parity_en : out vl_logic; receive_full : out vl_logic; rx_byte : out vl_logic_vector(7 downto 0); fifo_write : out vl_logic );end Rx_async;
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