library verilog;use verilog.vl_types.all;entity Clock_gen is    port(        clk             : in     vl_logic;        reset_n         : in     vl_logic;        baud_val        : in     vl_logic_vector(7 downto 0);        baud_clock      : out    vl_logic;        xmit_pulse      : out    vl_logic    );end Clock_gen;