<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREUART</name><vendor>Actel</vendor><library>DirectCore</library><version>3.1.103</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>coreparameters.v</name><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/></vendorExtensions></file><file fileid="1"><name>rtl\vlog\test\verif\testbnch.v</name><fileType>verilogSource</fileType><vendorExtensions><ModuleUnderTest>testbnch</ModuleUnderTest><SimulationTime>-all</SimulationTime></vendorExtensions></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="2"><name>mti\scripts\wave_vlog.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="3"><name>coreparameters.v</name><fileType>verilogSource</fileType></file><file fileid="4"><name>rtl\vlog\core_obfuscated\Clock_gen.v</name><fileType>verilogSource</fileType></file><file fileid="5"><name>rtl\vlog\core_obfuscated\Rx_async.v</name><fileType>verilogSource</fileType></file><file fileid="6"><name>rtl\vlog\core_obfuscated\Tx_async.v</name><fileType>verilogSource</fileType></file><file fileid="7"><name>rtl\vlog\core_obfuscated\CoreUART.v</name><fileType>verilogSource</fileType></file><file fileid="8"><name>rtl\vlog\core_obfuscated\fifo_256x8_pa3.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><vendorExtensions><libraries><library><name>COREUART_LIB</name><path>mti/lib_vlog_obs/COREUART_LIB</path></library></libraries></vendorExtensions></Component>