#add_file options
add_file -verilog "E:/所有其他/安裝文件/FPGA/actel/實驗例程/UART/hdl/rec.v"
add_file -verilog "E:/所有其他/安裝文件/FPGA/actel/實驗例程/UART/hdl/send.v"
add_file -verilog "E:/所有其他/安裝文件/FPGA/actel/實驗例程/UART/hdl/uart_test.v"

#device options
set_option -technology ProASIC3
set_option -part A3P250




#implementation: "synthesis"
impl -add synthesis -type fpga

set_option -speed_grade -2
#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 100.000
set_option -run_prop_extract 1
set_option -fanout_limit 12
set_option -globalthreshold 50
set_option -maxfan_hard 0
set_option -retiming 0
set_option -report_path 4000
set_option -opcond Default
set_option -update_models_cp 0
set_option -preserve_registers 0
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_format "edif"
impl -active "synthesis"
project -result_file "E:/所有其他/安裝文件/FPGA/actel/實驗例程/UART/synthesis/uart_test.edn"