EDA Netlist Writer report for sram_test
Thu Feb 12 09:21:16 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Simulation Settings
  4. Simulation Generated Files
  5. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------+
; EDA Netlist Writer Summary                                        ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Thu Feb 12 09:21:16 2009 ;
; Revision Name             ; sram_test                             ;
; Top-level Entity Name     ; sram_test                             ;
; Family                    ; MAX II                                ;
; Simulation Files Creation ; Successful                            ;
+---------------------------+---------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Simulation Settings                                                                                             ;
+--------------------------------------------------------------------------------------------+--------------------+
; Option                                                                                     ; Setting            ;
+--------------------------------------------------------------------------------------------+--------------------+
; Tool Name                                                                                  ; ModelSim (Verilog) ;
; Generate netlist for functional simulation only                                            ; Off                ;
; Time scale                                                                                 ; 1 ps               ;
; Truncate long hierarchy paths                                                              ; Off                ;
; Map illegal HDL characters                                                                 ; Off                ;
; Flatten buses into individual nodes                                                        ; Off                ;
; Maintain hierarchy                                                                         ; Off                ;
; Bring out device-wide set/reset signals as ports                                           ; Off                ;
; Enable glitch filtering                                                                    ; Off                ;
; Do not write top level VHDL entity                                                         ; Off                ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off                ;
; Architecture name in VHDL output netlist                                                   ; structure          ;
+--------------------------------------------------------------------------------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Simulation Generated Files                                                                                      ;
+-----------------------------------------------------------------------------------------------------------------+
; Generated Files                                                                                                 ;
+-----------------------------------------------------------------------------------------------------------------+
; C:/franchiese/GR/實驗例程備份/實驗例程以及說明文檔/11、讀寫SRAM/verilogsram/simulation/modelsim/sram_test.vo    ;
; C:/franchiese/GR/實驗例程備份/實驗例程以及說明文檔/11、讀寫SRAM/verilogsram/simulation/modelsim/sram_test_v.sdo ;
+-----------------------------------------------------------------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Thu Feb 12 09:21:15 2009
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off sram_test -c sram_test
Info: Generated files "sram_test.vo" and "sram_test_v.sdo" in directory "C:/franchiese/GR/實驗例程備份/實驗例程以及說明文檔/11、讀寫SRAM/verilogsram/simulation/modelsim/" for EDA simulation tool
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 119 megabytes
    Info: Processing ended: Thu Feb 12 09:21:16 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01