{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 12 09:21:02 2009 " "Info: Processing started: Thu Feb 12 09:21:02 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sram_test -c sram_test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sram_test -c sram_test" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sram_test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file sram_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 sram_test " "Info: Found entity 1: sram_test" {  } { { "sram_test.v" "" { Text "C:/franchiese/GR/實驗例程備份/實驗例程以及說明文檔/11、讀寫SRAM/verilogsram/sram_test.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sram_test " "Info: Elaborating entity \"sram_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 sram_test.v(40) " "Warning (10230): Verilog HDL assignment warning at sram_test.v(40): truncated value with size 32 to match size of target (26)" {  } { { "sram_test.v" "" { Text "C:/franchiese/GR/實驗例程備份/實驗例程以及說明文檔/11、讀寫SRAM/verilogsram/sram_test.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "sram_test.v(119) " "Info (10264): Verilog HDL Case Statement information at sram_test.v(119): all case item expressions in this case statement are onehot" {  } { { "sram_test.v" "" { Text "C:/franchiese/GR/實驗例程備份/實驗例程以及說明文檔/11、讀寫SRAM/verilogsram/sram_test.v" 119 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 3 " "Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cstate~14 " "Info: Register \"cstate~14\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cstate~15 " "Info: Register \"cstate~15\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cstate~17 " "Info: Register \"cstate~17\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "116 " "Info: Implemented 116 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "89 " "Info: Implemented 89 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "165 " "Info: Peak virtual memory: 165 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 12 09:21:04 2009 " "Info: Processing ended: Thu Feb 12 09:21:04 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}