library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity gray_counter is
generic (m : integer := 3);
port ( 
      reset    : in  std_logic;
      clk      : in  std_logic;
      gray_cnt : out std_logic_vector(m downto 0)
     );
end gray_counter;

architecture str of gray_counter is

  component gray_to_bin is
  generic (n : integer := 3);
  port ( reset : in  std_logic;
	     gray  : in  std_logic_vector(n downto 0);
	     bin   : out std_logic_vector(n downto 0) ); 
  end component;
  component bin_cnt is
  generic (n : integer := 3);
  port ( clk     : in  std_logic; 
         bin_in  : in  std_logic_vector(n downto 0);
         bin_cnt : out std_logic_vector(n downto 0) );
  end component;
  component bin_to_gray is
  generic (n : integer := 3);
  port ( reset : in  std_logic;
	     bin   : in  std_logic_vector(n downto 0);
	     gray  : out std_logic_vector(n downto 0) ); 
  end component; 

  signal gray,bin_in,bin_out : std_logic_vector(m downto 0); 
 
begin
  
  u1 : gray_to_bin 
       generic map (n => m)
       port map (reset,gray,bin_in);
  u2 : bin_cnt 
       generic map (n => m)   
       port map (clk,bin_in,bin_out);
  u3 : bin_to_gray 
       generic map (n => m)
       port map (reset,bin_out,gray);
  gray_cnt <= gray;

end str;