//`include "reg8.v"
module filter(out_data,in_data,clk);
output[9:0] out_data;
input [7:0] in_data;
input clk;

//reg[9:0] out_data;
wire clr,en;
assign en=1;assign clr=0;

reg[7:0] in_data1;
wire[7:0] in_data2,in_data3,in_data4;
wire[7:0] in_data5,in_data6,in_data7;
//wire[7:0] in_data8,in_data9,in_data10;

wire[8:0] add8_wire1,add8_wire2;
wire[7:0] add8_auxiliary;
wire[9:0] add9_out;

wire count3_1;

always @(posedge clk) 
begin
  in_data1[7:0]<=in_data;
end

reg8 reg8_11(.out_data(in_data2),.in_data(in_data1),.clk(clk),.clr(clr));
reg8 reg8_12(.out_data(in_data3),.in_data(in_data2),.clk(clk),.clr(clr));
reg8 reg8_13(.out_data(in_data4),.in_data(in_data3),.clk(clk),.clr(clr));

count3 count31(.cout(count3_1),.en(en),.clr(clr),.clk(clk));
reg8 reg8_21(.out_data(in_data5),.in_data(in_data2),.clk(count3_1),.clr(clr));
reg8 reg8_22(.out_data(in_data6),.in_data(in_data3),.clk(count3_1),.clr(clr));
reg8 reg8_23(.out_data(in_data7),.in_data(in_data4),.clk(count3_1),.clr(clr));

//reg8 reg8_31(.out_data(in_data8),.in_data(in_data5),clk(count3_1),clr(clr));
//reg8 reg8_32(.out_data(in_data9),.in_data(in_data6),clk(count3_1),clr(clr));
//reg8 reg8_33(.out_data(in_data10),.in_data(in_data7),clk(count3_1),clr(clr));
add8_9 add8_91(.x(in_data5), .y(in_data6), .sum(add8_wire1), .clk(count3_1));
assign add8_auxiliary={8{1'b0}};
add8_9 add8_92(.x(in_data7), .y(add8_auxiliary), .sum(add8_wire2), .clk(count3_1));

add_1p add9(.x(add8_wire1),.y(add8_wire2), .sum(add9_out),.clk(count3_1));
 defparam add9.WIDTH= 9;
 defparam add9.WIDTH1=7;
 defparam add9.WIDTH2=2;
 
 assign out_data=add9_out;

endmodule