?? filter.map.rpt
字號:
Analysis & Synthesis report for filter
Mon Feb 23 19:22:58 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis RAM Summary
8. Registers Removed During Synthesis
9. Removed Registers Triggering Further Register Optimizations
10. General Register Statistics
11. Source assignments for reg8:reg8_23|altshift_taps:out_data_rtl_0|shift_taps_c0m:auto_generated|altsyncram_e681:altsyncram2
12. Parameter Settings for User Entity Instance: add8_9:add8_91
13. Parameter Settings for User Entity Instance: add8_9:add8_91|lpm_add_sub:add_1
14. Parameter Settings for User Entity Instance: add8_9:add8_92
15. Parameter Settings for User Entity Instance: add8_9:add8_92|lpm_add_sub:add_1
16. Parameter Settings for User Entity Instance: add_1p:add9
17. Parameter Settings for User Entity Instance: add_1p:add9|lpm_add_sub:add_1
18. Parameter Settings for User Entity Instance: add_1p:add9|lpm_ff:reg_1
19. Parameter Settings for User Entity Instance: add_1p:add9|lpm_ff:reg_2
20. Parameter Settings for User Entity Instance: add_1p:add9|lpm_add_sub:add_2
21. Parameter Settings for User Entity Instance: add_1p:add9|lpm_ff:reg_3
22. Parameter Settings for User Entity Instance: add_1p:add9|lpm_ff:reg_4
23. Parameter Settings for User Entity Instance: add_1p:add9|lpm_add_sub:add_3
24. Parameter Settings for Inferred Entity Instance: reg8:reg8_23|altshift_taps:out_data_rtl_0
25. altshift_taps Parameter Settings by Entity Instance
26. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Feb 23 19:22:58 2009 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Web Edition ;
; Revision Name ; filter ;
; Top-level Entity Name ; filter ;
; Family ; Cyclone II ;
; Total logic elements ; 106 ;
; Total combinational functions ; 26 ;
; Dedicated logic registers ; 106 ;
; Total registers ; 106 ;
; Total pins ; 19 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 16 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+-----------------------------------------+
+----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C35F672C6 ; ;
; Top-level entity name ; filter ; filter ;
; Family name ; Cyclone II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
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