?? filter.map.rpt
字號:
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+----------------------------------------------------------------+--------------------+--------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+
; reg8.v ; yes ; User Verilog HDL File ; F:/sopc/lunwen/filter/reg8.v ;
; filter.v ; yes ; User Verilog HDL File ; F:/sopc/lunwen/filter/filter.v ;
; count3.v ; yes ; User Verilog HDL File ; F:/sopc/lunwen/filter/count3.v ;
; add8_9.v ; yes ; User Verilog HDL File ; F:/sopc/lunwen/filter/add8_9.v ;
; add_1p .v ; yes ; User Verilog HDL File ; F:/sopc/lunwen/filter/add_1p .v ;
; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/lpm_add_sub.tdf ;
; addcore.inc ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/addcore.inc ;
; look_add.inc ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/look_add.inc ;
; bypassff.inc ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/altshift.inc ;
; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal81.inc ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/aglobal81.inc ;
; db/add_sub_rjc.tdf ; yes ; Auto-Generated Megafunction ; F:/sopc/lunwen/filter/db/add_sub_rjc.tdf ;
; db/add_sub_qjc.tdf ; yes ; Auto-Generated Megafunction ; F:/sopc/lunwen/filter/db/add_sub_qjc.tdf ;
; lpm_ff.tdf ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/lpm_ff.tdf ;
; lpm_constant.inc ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/lpm_constant.inc ;
; db/add_sub_ljc.tdf ; yes ; Auto-Generated Megafunction ; F:/sopc/lunwen/filter/db/add_sub_ljc.tdf ;
; db/add_sub_urc.tdf ; yes ; Auto-Generated Megafunction ; F:/sopc/lunwen/filter/db/add_sub_urc.tdf ;
; altshift_taps.tdf ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/altshift_taps.tdf ;
; altdpram.inc ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/altdpram.inc ;
; lpm_counter.inc ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/lpm_counter.inc ;
; lpm_compare.inc ; yes ; Megafunction ; c:/altera/81/quartus/libraries/megafunctions/lpm_compare.inc ;
; db/shift_taps_c0m.tdf ; yes ; Auto-Generated Megafunction ; F:/sopc/lunwen/filter/db/shift_taps_c0m.tdf ;
; db/altsyncram_e681.tdf ; yes ; Auto-Generated Megafunction ; F:/sopc/lunwen/filter/db/altsyncram_e681.tdf ;
; db/cntr_ikf.tdf ; yes ; Auto-Generated Megafunction ; F:/sopc/lunwen/filter/db/cntr_ikf.tdf ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+
+---------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-----------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------+
; Estimated Total logic elements ; 106 ;
; ; ;
; Total combinational functions ; 26 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 18 ;
; -- <=2 input functions ; 8 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 11 ;
; -- arithmetic mode ; 15 ;
; ; ;
; Total registers ; 106 ;
; -- Dedicated logic registers ; 106 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 19 ;
; Total memory bits ; 16 ;
; Maximum fan-out node ; count3:count31|Equal0 ;
; Maximum fan-out ; 82 ;
; Total fan-out ; 312 ;
; Average fan-out ; 1.96 ;
+---------------------------------------------+-----------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------+--------------+
; |filter ; 26 (0) ; 106 (8) ; 16 ; 0 ; 0 ; 0 ; 19 ; 0 ; |filter ; work ;
; |add8_9:add8_91| ; 9 (9) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|add8_9:add8_91 ; work ;
; |add_1p:add9| ; 13 (0) ; 30 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|add_1p:add9 ; work ;
; |lpm_add_sub:add_2| ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|add_1p:add9|lpm_add_sub:add_2 ; work ;
; |add_sub_ljc:auto_generated| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated ; work ;
; |lpm_add_sub:add_3| ; 2 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|add_1p:add9|lpm_add_sub:add_3 ; work ;
; |add_sub_urc:auto_generated| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|add_1p:add9|lpm_add_sub:add_3|add_sub_urc:auto_generated ; work ;
; |lpm_ff:reg_1| ; 7 (7) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|add_1p:add9|lpm_ff:reg_1 ; work ;
; |lpm_ff:reg_2| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|add_1p:add9|lpm_ff:reg_2 ; work ;
; |lpm_ff:reg_3| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|add_1p:add9|lpm_ff:reg_3 ; work ;
; |lpm_ff:reg_4| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|add_1p:add9|lpm_ff:reg_4 ; work ;
; |count3:count31| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|count3:count31 ; work ;
; |reg8:reg8_11| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|reg8:reg8_11 ; work ;
; |reg8:reg8_12| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|reg8:reg8_12 ; work ;
; |reg8:reg8_13| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|reg8:reg8_13 ; work ;
; |reg8:reg8_21| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|reg8:reg8_21 ; work ;
; |reg8:reg8_22| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|reg8:reg8_22 ; work ;
; |reg8:reg8_23| ; 1 (0) ; 1 (0) ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|reg8:reg8_23 ; work ;
; |altshift_taps:out_data_rtl_0| ; 1 (0) ; 1 (0) ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|reg8:reg8_23|altshift_taps:out_data_rtl_0 ; work ;
; |shift_taps_c0m:auto_generated| ; 1 (0) ; 1 (0) ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|reg8:reg8_23|altshift_taps:out_data_rtl_0|shift_taps_c0m:auto_generated ; work ;
; |altsyncram_e681:altsyncram2| ; 0 (0) ; 0 (0) ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|reg8:reg8_23|altshift_taps:out_data_rtl_0|shift_taps_c0m:auto_generated|altsyncram_e681:altsyncram2 ; work ;
; |cntr_ikf:cntr1| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |filter|reg8:reg8_23|altshift_taps:out_data_rtl_0|shift_taps_c0m:auto_generated|cntr_ikf:cntr1 ; work ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+----------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+----------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; reg8:reg8_23|altshift_taps:out_data_rtl_0|shift_taps_c0m:auto_generated|altsyncram_e681:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 2 ; 8 ; 2 ; 8 ; 16 ; None ;
+----------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+----------------------------------------+
; add8_9:add8_92|l2[0..7] ; Stuck at GND due to stuck port data_in ;
; add8_9:add8_92|s[8] ; Stuck at GND due to stuck port data_in ;
; add_1p:add9|l4[1] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 10 ; ;
+----------------------------------------+----------------------------------------+
+-------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+----------------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+----------------------+---------------------------+----------------------------------------+
; add8_9:add8_92|l2[3] ; Stuck at GND ; add8_9:add8_92|s[8], add_1p:add9|l4[1] ;
; ; due to stuck port data_in ; ;
+----------------------+---------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
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