module reg_give(out_data,in_data,clk,clr);
parameter WIDTH = 10; // Total bit width

output[WIDTH :0] out_data;
input [WIDTH :0] in_data;
input clk,clr;                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                

reg[WIDTH :0] out_data;
always @(posedge clk or posedge clr)
 begin 
   if(clr)  out_data<=0;
   else     out_data<=in_data;
 end
endmodule