{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Web Edition " "Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 23 19:22:49 2009 " "Info: Processing started: Mon Feb 23 19:22:49 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off filter -c filter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off filter -c filter" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg8.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file reg8.v" { { "Info" "ISGN_ENTITY_NAME" "1 reg8 " "Info: Found entity 1: reg8" {  } { { "reg8.v" "" { Text "F:/sopc/lunwen/filter/reg8.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "filter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file filter.v" { { "Info" "ISGN_ENTITY_NAME" "1 filter " "Info: Found entity 1: filter" {  } { { "filter.v" "" { Text "F:/sopc/lunwen/filter/filter.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count3.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file count3.v" { { "Info" "ISGN_ENTITY_NAME" "1 count3 " "Info: Found entity 1: count3" {  } { { "count3.v" "" { Text "F:/sopc/lunwen/filter/count3.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add8_9.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file add8_9.v" { { "Info" "ISGN_ENTITY_NAME" "1 add8_9 " "Info: Found entity 1: add8_9" {  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_1p .v 1 1 " "Info: Found 1 design units, including 1 entities, in source file add_1p .v" { { "Info" "ISGN_ENTITY_NAME" "1 add_1p " "Info: Found entity 1: add_1p" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "filter " "Info: Elaborating entity \"filter\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg8 reg8:reg8_11 " "Info: Elaborating entity \"reg8\" for hierarchy \"reg8:reg8_11\"" {  } { { "filter.v" "reg8_11" { Text "F:/sopc/lunwen/filter/filter.v" 27 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count3 count3:count31 " "Info: Elaborating entity \"count3\" for hierarchy \"count3:count31\"" {  } { { "filter.v" "count31" { Text "F:/sopc/lunwen/filter/filter.v" 31 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 count3.v(12) " "Warning (10230): Verilog HDL assignment warning at count3.v(12): truncated value with size 32 to match size of target (2)" {  } { { "count3.v" "" { Text "F:/sopc/lunwen/filter/count3.v" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 count3.v(15) " "Warning (10230): Verilog HDL assignment warning at count3.v(15): truncated value with size 32 to match size of target (1)" {  } { { "count3.v" "" { Text "F:/sopc/lunwen/filter/count3.v" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add8_9 add8_9:add8_91 " "Info: Elaborating entity \"add8_9\" for hierarchy \"add8_9:add8_91\"" {  } { { "filter.v" "add8_91" { Text "F:/sopc/lunwen/filter/filter.v" 39 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "clkena add8_9.v(16) " "Warning (10036): Verilog HDL or VHDL warning at add8_9.v(16): object \"clkena\" assigned a value but never read" {  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 16 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ADD add8_9.v(16) " "Warning (10036): Verilog HDL or VHDL warning at add8_9.v(16): object \"ADD\" assigned a value but never read" {  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 16 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ena add8_9.v(16) " "Warning (10036): Verilog HDL or VHDL warning at add8_9.v(16): object \"ena\" assigned a value but never read" {  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 16 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "aset add8_9.v(16) " "Warning (10036): Verilog HDL or VHDL warning at add8_9.v(16): object \"aset\" assigned a value but never read" {  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 16 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sclr add8_9.v(16) " "Warning (10036): Verilog HDL or VHDL warning at add8_9.v(16): object \"sclr\" assigned a value but never read" {  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 16 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sset add8_9.v(17) " "Warning (10036): Verilog HDL or VHDL warning at add8_9.v(17): object \"sset\" assigned a value but never read" {  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "aload add8_9.v(17) " "Warning (10036): Verilog HDL or VHDL warning at add8_9.v(17): object \"aload\" assigned a value but never read" {  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sload add8_9.v(17) " "Warning (10036): Verilog HDL or VHDL warning at add8_9.v(17): object \"sload\" assigned a value but never read" {  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "aclr add8_9.v(17) " "Warning (10036): Verilog HDL or VHDL warning at add8_9.v(17): object \"aclr\" assigned a value but never read" {  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cin1 add8_9.v(17) " "Warning (10036): Verilog HDL or VHDL warning at add8_9.v(17): object \"cin1\" assigned a value but never read" {  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 17 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub add8_9:add8_91\|lpm_add_sub:add_1 " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"add8_9:add8_91\|lpm_add_sub:add_1\"" {  } { { "add8_9.v" "add_1" { Text "F:/sopc/lunwen/filter/add8_9.v" 34 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "add8_9:add8_91\|lpm_add_sub:add_1 " "Info: Elaborated megafunction instantiation \"add8_9:add8_91\|lpm_add_sub:add_1\"" {  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 34 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "add8_9:add8_91\|lpm_add_sub:add_1 " "Info: Instantiated megafunction \"add8_9:add8_91\|lpm_add_sub:add_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Info: Parameter \"lpm_width\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction add " "Info: Parameter \"lpm_direction\" = \"add\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "add8_9.v" "" { Text "F:/sopc/lunwen/filter/add8_9.v" 34 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_rjc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_rjc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_rjc " "Info: Found entity 1: add_sub_rjc" {  } { { "db/add_sub_rjc.tdf" "" { Text "F:/sopc/lunwen/filter/db/add_sub_rjc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_rjc add8_9:add8_91\|lpm_add_sub:add_1\|add_sub_rjc:auto_generated " "Info: Elaborating entity \"add_sub_rjc\" for hierarchy \"add8_9:add8_91\|lpm_add_sub:add_1\|add_sub_rjc:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/81/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_1p add_1p:add9 " "Info: Elaborating entity \"add_1p\" for hierarchy \"add_1p:add9\"" {  } { { "filter.v" "add9" { Text "F:/sopc/lunwen/filter/filter.v" 43 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "clkena add_1p .v(19) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(19): object \"clkena\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 19 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ADD add_1p .v(19) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(19): object \"ADD\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 19 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ena add_1p .v(19) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(19): object \"ena\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 19 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "aset add_1p .v(19) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(19): object \"aset\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 19 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sclr add_1p .v(19) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(19): object \"sclr\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 19 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "sset add_1p .v(20) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(20): object \"sset\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 20 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "aload add_1p .v(20) " "Warning (10036): Verilog HDL or VHDL warning at add_1p .v(20): object \"aload\" assigned a value but never read" {  } { { "add_1p .v" "" { Text "F:/sopc/lunwen/filter/add_1p .v" 20 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}