?? edge.sim.rpt
字號(hào):
; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;
; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;
; Overwrite Waveform Inputs With Simulation Outputs ; On ; ;
; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;
+--------------------------------------------------------------------------------------------+------------+---------------+
+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.
+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 87.21 % ;
; Total nodes checked ; 937 ;
; Total output ports checked ; 1063 ;
; Total output ports with complete 1/0-value coverage ; 927 ;
; Total output ports with no 1/0-value coverage ; 81 ;
; Total output ports with no 1-value coverage ; 90 ;
; Total output ports with no 0-value coverage ; 127 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+---------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+------------------+
; |edge|out_data1[9] ; |edge|out_data1[9] ; pin_out ;
; |edge|out_data1[8] ; |edge|out_data1[8] ; pin_out ;
; |edge|out_data1[7] ; |edge|out_data1[7] ; pin_out ;
; |edge|out_data1[6] ; |edge|out_data1[6] ; pin_out ;
; |edge|out_data1[5] ; |edge|out_data1[5] ; pin_out ;
; |edge|out_data1[4] ; |edge|out_data1[4] ; pin_out ;
; |edge|out_data1[3] ; |edge|out_data1[3] ; pin_out ;
; |edge|out_data1[2] ; |edge|out_data1[2] ; pin_out ;
; |edge|clk ; |edge|clk ; out ;
; |edge|in_data1[6] ; |edge|in_data1[6] ; out ;
; |edge|in_data1[5] ; |edge|in_data1[5] ; out ;
; |edge|in_data1[4] ; |edge|in_data1[4] ; out ;
; |edge|in_data1[3] ; |edge|in_data1[3] ; out ;
; |edge|in_data1[2] ; |edge|in_data1[2] ; out ;
; |edge|in_data1[1] ; |edge|in_data1[1] ; out ;
; |edge|in_data1[0] ; |edge|in_data1[0] ; out ;
; |edge|in_data2[6] ; |edge|in_data2[6] ; out ;
; |edge|in_data2[5] ; |edge|in_data2[5] ; out ;
; |edge|in_data2[4] ; |edge|in_data2[4] ; out ;
; |edge|in_data2[3] ; |edge|in_data2[3] ; out ;
; |edge|in_data2[2] ; |edge|in_data2[2] ; out ;
; |edge|in_data2[1] ; |edge|in_data2[1] ; out ;
; |edge|in_data2[0] ; |edge|in_data2[0] ; out ;
; |edge|in_data3[7] ; |edge|in_data3[7] ; out ;
; |edge|in_data3[6] ; |edge|in_data3[6] ; out ;
; |edge|in_data3[5] ; |edge|in_data3[5] ; out ;
; |edge|in_data3[4] ; |edge|in_data3[4] ; out ;
; |edge|in_data3[3] ; |edge|in_data3[3] ; out ;
; |edge|in_data3[2] ; |edge|in_data3[2] ; out ;
; |edge|in_data3[1] ; |edge|in_data3[1] ; out ;
; |edge|out_data2[21] ; |edge|out_data2[21] ; pin_out ;
; |edge|out_data2[20] ; |edge|out_data2[20] ; pin_out ;
; |edge|out_data2[19] ; |edge|out_data2[19] ; pin_out ;
; |edge|out_data2[18] ; |edge|out_data2[18] ; pin_out ;
; |edge|out_data2[17] ; |edge|out_data2[17] ; pin_out ;
; |edge|out_data2[16] ; |edge|out_data2[16] ; pin_out ;
; |edge|out_data2[12] ; |edge|out_data2[12] ; pin_out ;
; |edge|out_data2[11] ; |edge|out_data2[11] ; pin_out ;
; |edge|out_data2[10] ; |edge|out_data2[10] ; pin_out ;
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