; Device                                                             ; EP2C35F672C6                   ;                                ;
; Minimum Core Junction Temperature                                  ; 0                              ;                                ;
; Maximum Core Junction Temperature                                  ; 85                             ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                  ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Maximum number of global clocks allowed                            ; -1                             ; -1                             ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Fitter Partition Preservation Settings                                                                 ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Name ; # Preserved Nodes ; # Nodes ; Preservation Level Requested ; Netlist Type Used      ; Hierarchy ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Top  ; 0                 ; 267     ; Placement and Routing        ; Post-Synthesis Netlist ;           ;
+------+-------------------+---------+------------------------------+------------------------+-----------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/jeffie/final/lcdfinal/lcdfinal.pin.


+-------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                       ;
+---------------------------------------------+---------------------------------------+
; Resource                                    ; Usage                                 ;
+---------------------------------------------+---------------------------------------+
; Total logic elements                        ; 120 / 33,216 ( < 1 % )                ;
;     -- Combinational with no register       ; 48                                    ;
;     -- Register only                        ; 0                                     ;
;     -- Combinational with a register        ; 72                                    ;
;                                             ;                                       ;
; Logic element usage by number of LUT inputs ;                                       ;
;     -- 4 input functions                    ; 52                                    ;
;     -- 3 input functions                    ; 14                                    ;
;     -- <=2 input functions                  ; 54                                    ;
;     -- Register only                        ; 0                                     ;
;                                             ;                                       ;
; Logic elements by mode                      ;                                       ;
;     -- normal mode                          ; 77                                    ;
;     -- arithmetic mode                      ; 43                                    ;
;                                             ;                                       ;
; Total registers*                            ; 72 / 34,593 ( < 1 % )                 ;
;     -- Dedicated logic registers            ; 72 / 33,216 ( < 1 % )                 ;
;     -- I/O registers                        ; 0 / 1,377 ( 0 % )                     ;
;                                             ;                                       ;
; Total LABs:  partially or completely used   ; 10 / 2,076 ( < 1 % )                  ;
; User inserted logic elements                ; 0                                     ;
; Virtual pins                                ; 0                                     ;
; I/O pins                                    ; 75 / 475 ( 16 % )                     ;
;     -- Clock pins                           ; 4 / 8 ( 50 % )                        ;
; Global signals                              ; 2                                     ;