以下是3分頻的Verilog代碼，覺得挺有用。
module Div_3.v(out_clk,in_clk,clr);
       output   out_clk;
       input    in_clk,clr;
       reg      out_clk;
       reg      p_clk,n_clk;
       reg[2:0]   counter;
       assign  out_clk = p_clk | n_clk;
       always@ (posedge in_clk or negedge clr)
           begin
              if(!clr)
                 out_clk <= 0;
              else
                 counter <= (counter == 2)?0 : (counter + 1);
           end
       always@(posedge  in_clk or negedge clr)
            begin
                if(!clr)
                  p_clk <= 0;
                else
                   if(counter < 1)
                        p_clk <= 1;
                   else
                        p_clk <= 0;
             end
        always@(negdge in_clk or clr)
            begin
               if(!clr)
                   n_clk <= 0;
               else
                    if(counter < 1)
                        n_clk <= 1;
                    else 
                        n_clk <= 0;
             end
endmodule









函數(shù)發(fā)生器，其Verilog代碼如下 
module  ls138(Y,A,reset); 
     output[70]   Y; 
     input[20]    A; 
     input        reset; 
     reg[70]      Y; 
     wire[20]      A; 
     [email=always@(A]always@(A[email] or reset) 
       begin 
         case(A) 
            0  Y = 8'b1111_1110; 
            1  Y = 8'b1111_1101; 
            2  Y = 8'b1111_1011; 
            3  Y = 8'b1111_0111; 
            4  Y = 8'b1110_1111; 
            5  Y = 8'b1101_1111; 
            6  Y = 8'b1011_1111; 
            7  Y = 8'b0111_1111; 
            default  Y = 8'b1111_1111; 
         endcase 
       end 
endmodule 
module fuction_0(D,K,reset); 
     output[20]   D; 
     input[20]    K; 
     input         reset; 
     wire[70]      Y; 
     wire[20]     A; 
     assign  A = K; 
     ls138 u1(.Y(Y),.A(A),.reset(reset)); 
     nand  u2(D[2],Y[6],Y[5],Y[4],Y[3]); 
     nand  u3(D[1],Y[7],Y[3],Y[1]); 
     nand  u4(D[0],Y[5],Y[3],Y[2]); 
endmodule 




//時鐘RS觸發(fā)器
module part1(R,S,CLK,Q); 
   input R,S,CLK; 
   output Q; 
   wire R_gate,S_gate,Qa,Qb; 
   and  u1(R_gate,R,CLK); 
   and  u2(S_gate,S,CLK); 
   nor  u3(Qa,R_gate,Qb); 
   nor  u4(Qb,S_gate,Qa); 

   assign Q = Qa; 
endmodule 







//8位加法器
module Flip_Flop_T(Q,T,Clock);
output Q;
input T,Clock;
reg  Q;
[email=always@(posedge]always@(posedge[/email] Clock )
  begin
    if(T == 1)
     Q <= ~Q;
    else
     Q <= Q;
  end
endmodule 
module Counter_T(Enable,Clock,Q);
input Enable;
input Clock;
output[7:0] Q;
wire[7:0] Q;
wire[6:0] T_In_Temp;
   Flip_Flop_T  u1(.T(Enable),.Clock(Clock),.Q(Q[0]));
   assign T_In_Temp[0] = Enable & Q[0];
   Flip_Flop_T  u2(.T(T_In_Temp[0]),.Clock(Clock),.Q(Q[1]));
   assign T_In_Temp[1] = T_In_Temp[0] & Q[1];
   Flip_Flop_T  u3(.T(T_In_Temp[1]),.Clock(Clock),.Q(Q[2]));
   assign T_In_Temp[2] = T_In_Temp[1] & Q[2];
   Flip_Flop_T  u4(.T(T_In_Temp[2]),.Clock(Clock),.Q(Q[3]));
   assign T_In_Temp[3] = T_In_Temp[2] & Q[3];
   Flip_Flop_T  u5(.T(T_In_Temp[3]),.Clock(Clock),.Q(Q[4]));
   assign T_In_Temp[4] = T_In_Temp[3] & Q[4];
   Flip_Flop_T  u6(.T(T_In_Temp[4]),.Clock(Clock),.Q(Q[5]));
   assign T_In_Temp[5] = T_In_Temp[4] & Q[5];
   Flip_Flop_T  u7(.T(T_In_Temp[5]),.Clock(Clock),.Q(Q[6]));
   assign T_In_Temp[6] = T_In_Temp[5] & Q[6];
   Flip_Flop_T  u8(.T(T_In_Temp[6]),.Clock(Clock),.Q(Q[7]));
endmodule