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-- Company: 
-- Engineer:
--
-- Create Date:    17:38:37 03/13/09
-- Design Name:    
-- Module Name:    baud - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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--說明：由一個分頻器組成，將外部輸入的32MHz的信號分成頻率為153600Hz的信號
--最后修改時間：2003年7月10日
--===============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity baud is
    Port (clk	 :in std_logic;
	       resetb:in std_logic;
          bclk  :out std_logic);
end baud;
 
architecture behavioral of baud is

signal bclkout:std_logic;

begin
process(clk,resetb)
variable cnt:integer;
begin
  if resetb='1' then                                         -- resetb='1'時復位
     cnt:=0; bclkout<='0';
  elsif rising_edge(clk) then
     if cnt>=1 then cnt:=0; bclkout<=not bclkout;                        --設置分頻系數
         else cnt:=cnt+1;
         end if;
  end if;
end process;
bclk<=bclkout;
end behavioral;