library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_SIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity MedFilter_VHD isport(	clk 	: in std_logic;	rst 	: in std_logic;	nd 	: in std_logic;	din	: in std_logic_Vector(15 downto 0);------	rdy 	: out std_logic;	dout  :out std_logic_VEctor(15 downto 0));end MedFilter_VHD;
--Median Filter VHD Create by mike.chen 20090315
--derived form Matlab Medfilt1 Function
--inplement Odd 3 tap
--y = medfilt1(x,n) 
--y(k) is the median of x(k-(n-1)/2:k+(n-1)/2)
architecture Behavioral of MedFilter_VHD is--type array3x16bits is array(2 downto 0) of std_logic_vector(15 downto 0);--signal dline_vector1 : array3x16bits:=(others=>(others=>'0'));
signal dline_A 			: std_logic_vector(15 downto 0):=(others=>'0');
signal dline_B 			: std_logic_vector(15 downto 0):=(others=>'0');
signal dline_C 			: std_logic_vector(15 downto 0):=(others=>'0');
signal dline_Ar 			: std_logic_vector(15 downto 0):=(others=>'0');
signal dline_Br 			: std_logic_vector(15 downto 0):=(others=>'0');
signal dline_Cr 			: std_logic_vector(15 downto 0):=(others=>'0');
signal A_big_equal_B 	: std_logic:='0';signal B_big_equal_C 	: std_logic:='0';signal A_big_equal_C 	: std_logic:='0';signal comparation_ABC  : std_logic_Vector(2 downto 0):=(others=>'0');signal nd1 					: std_logic;

beginprocess(rst,clk)begin
	if (rst = '1') then
		dline_C <=	(others=>'0');
		dline_B <=	(others=>'0');
		dline_A <=	(others=>'0');		elsif (clk'event and clk = '1') then
		if (nd = '1') then			dline_C <= din;
			dline_B <= dline_C;
			dline_A <= dline_B;	
		end if;	end if;end process;process(rst,clk)begin
	if (rst = '1') then
		A_big_equal_B	<='0';
		B_big_equal_C	<='0';
		A_big_equal_C	<='0';
		
		dline_Ar			<=	(others=>'0');
		dline_Br			<=	(others=>'0');
		dline_Cr			<=	(others=>'0');	
		elsif (clk'event and clk = '1') then
		if (nd = '1') then	
			if (dline_A >= dline_B) then
				A_big_equal_B <= '1';
			else
				A_big_equal_B <= '0';
			end if;
		
			if (dline_B >= dline_C) then
				B_big_equal_C <= '1';
			else
				B_big_equal_C <= '0';			
			end if;
		
			if (dline_A >= dline_C) then
				A_big_equal_C <= '1';
			else
				A_big_equal_C <= '0';			
			end if;
			
			dline_Ar	<= dline_A;
			dline_Br	<= dline_B;
			dline_Cr	<= dline_C;
		end if;	end if;end process;comparation_ABC <= A_big_equal_B & B_big_equal_C & A_big_equal_C;process(rst,clk)
begin
	if (rst = '1') then
		rdy  <= '0';
		dout <= (others=>'0');
	elsif (clk'event and clk = '1') then
	
		rdy <= nd;
		
		if (nd = '1') then
			case comparation_ABC is
				when "111" => --A>=B;B>=C;A>=C,Med value should be B
					dout <= dline_Br;
				when "101" => --A>=B;B<C;A>=C,Med value should be C
					dout <= dline_Cr;
				when "100" => --A>=B;B<C;A<C,Med value should be A
					dout <= dline_Ar;
				when "011" => --A<B;B>=C;A>=C,Med value should be A
					dout <= dline_Ar;
				when "010" => --A<B;B>=C;A<C,Med value should be C
					dout <= dline_Cr;
				when "000" => --A<B;B<C;A<C,Med value should be B
					dout <= dline_Br;			
				when others=> --A=B=C
					dout <= dline_Ar;
			end case;
		end if;
	end if;
end process;end Behavioral;