//=============================================================================
// File Name : 2410addr.h
// Function  : S3C2410 Define Address Register
// Program   : Shin, On Pil (SOP)
// Date      : May 06, 2002
// Version   : 0.0
// History
//   0.0 : Programming start (February 15,2002) -> SOP
//         INTERRUPT PRIORITY 0x4a00000a -> 0x4a00000c       (May 02, 2002 SOP)
//         RTC BCD DAY and DATE Register Name Correction      (May 06, 2002 SOP) 
//=============================================================================

#ifndef __S3C2410_H__
#define __S3C2410_H__

#ifdef __cplusplus
extern "C" {
#endif

/**
 * @addtogroup S3C2410
 */
/*@{*/

// Memory control 
#define BWSCON    (*(volatile unsigned *)0x48000000) //Bus width & wait status
#define BANKCON0  (*(volatile unsigned *)0x48000004) //Boot ROM control
#define BANKCON1  (*(volatile unsigned *)0x48000008) //BANK1 control
#define BANKCON2  (*(volatile unsigned *)0x4800000c) //BANK2 cControl
#define BANKCON3  (*(volatile unsigned *)0x48000010) //BANK3 control
#define BANKCON4  (*(volatile unsigned *)0x48000014) //BANK4 control
#define BANKCON5  (*(volatile unsigned *)0x48000018) //BANK5 control
#define BANKCON6  (*(volatile unsigned *)0x4800001c) //BANK6 control
#define BANKCON7  (*(volatile unsigned *)0x48000020) //BANK7 control
#define REFRESH   (*(volatile unsigned *)0x48000024) //DRAM/SDRAM efresh
#define BANKSIZE  (*(volatile unsigned *)0x48000028) //Flexible Bank Size
#define MRSRB6    (*(volatile unsigned *)0x4800002c) //Mode egister set for SDRAM
#define MRSRB7    (*(volatile unsigned *)0x48000030) //Mode egister set for SDRAM


// USB Host


// INTERRUPT
#define SRCPND     (*(volatile unsigned *)0x4a000000) //Interrupt request status
#define INTMOD     (*(volatile unsigned *)0x4a000004) //Interrupt mode control
#define INTMSK     (*(volatile unsigned *)0x4a000008) //Interrupt mask control
#define PRIORITY   (*(volatile unsigned *)0x4a00000c) //IRQ priority control
#define INTPND     (*(volatile unsigned *)0x4a000010) //Interrupt request status
#define INTOFFSET  (*(volatile unsigned *)0x4a000014) //Interruot request source offset
#define SUBSRCPND  (*(volatile unsigned *)0x4a000018) //Sub source pending
#define INTSUBMSK  (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask


// DMA
#define DISRC0     (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source
#define DISRCC0    (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
#define DIDST0     (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination
#define DIDSTC0    (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
#define DCON0      (*(volatile unsigned *)0x4b000010) //DMA 0 Control
#define DSTAT0     (*(volatile unsigned *)0x4b000014) //DMA 0 Status
#define DCSRC0     (*(volatile unsigned *)0x4b000018) //DMA 0 Current source
#define DCDST0     (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination
#define DMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger

#define DISRC1     (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source
#define DISRCC1    (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control
#define DIDST1     (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination
#define DIDSTC1    (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control
#define DCON1      (*(volatile unsigned *)0x4b000050) //DMA 1 Control
#define DSTAT1     (*(volatile unsigned *)0x4b000054) //DMA 1 Status
#define DCSRC1     (*(volatile unsigned *)0x4b000058) //DMA 1 Current source
#define DCDST1     (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination
#define DMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger

#define DISRC2     (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source
#define DISRCC2    (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control
#define DIDST2     (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination
#define DIDSTC2    (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control
#define DCON2      (*(volatile unsigned *)0x4b000090) //DMA 2 Control
#define DSTAT2     (*(volatile unsigned *)0x4b000094) //DMA 2 Status
#define DCSRC2     (*(volatile unsigned *)0x4b000098) //DMA 2 Current source
#define DCDST2     (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination
#define DMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger

#define DISRC3     (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source
#define DISRCC3    (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control
#define DIDST3     (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination
#define DIDSTC3    (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control
#define DCON3      (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control
#define DSTAT3     (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status
#define DCSRC3     (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source
#define DCDST3     (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination
#define DMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger


// CLOCK & POWER MANAGEMENT
#define LOCKTIME   (*(volatile unsigned *)0x4c000000) //PLL lock time counter
#define MPLLCON    (*(volatile unsigned *)0x4c000004) //MPLL Control
#define UPLLCON    (*(volatile unsigned *)0x4c000008) //UPLL Control
#define CLKCON     (*(volatile unsigned *)0x4c00000c) //Clock generator control
#define CLKSLOW    (*(volatile unsigned *)0x4c000010) //Slow clock control
#define CLKDIVN    (*(volatile unsigned *)0x4c000014) //Clock divider control
#define CAMDIVN    (*(volatile unsigned *)0x4c000018)	//USB, CAM Clock divider control


// LCD CONTROLLER
#define LCDCON1    (*(volatile unsigned *)0x4d000000) //LCD control 1
#define LCDCON2    (*(volatile unsigned *)0x4d000004) //LCD control 2
#define LCDCON3    (*(volatile unsigned *)0x4d000008) //LCD control 3
#define LCDCON4    (*(volatile unsigned *)0x4d00000c) //LCD control 4
#define LCDCON5    (*(volatile unsigned *)0x4d000010) //LCD control 5
#define LCDSADDR1  (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1
#define LCDSADDR2  (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2
#define LCDSADDR3  (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set
#define REDLUT     (*(volatile unsigned *)0x4d000020) //STN Red lookup table
#define GREENLUT   (*(volatile unsigned *)0x4d000024) //STN Green lookup table 
#define BLUELUT    (*(volatile unsigned *)0x4d000028) //STN Blue lookup table
#define DITHMODE   (*(volatile unsigned *)0x4d00004c) //STN Dithering mode
#define TPAL       (*(volatile unsigned *)0x4d000050) //TFT Temporary palette
#define LCDINTPND  (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending
#define LCDSRCPND  (*(volatile unsigned *)0x4d000058) //LCD Interrupt source
#define LCDINTMSK  (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask
#define LPCSEL     (*(volatile unsigned *)0x4d000060) //LPC3600 Control
#define PALETTE     0x4d000400                         //Palette start address


// NAND flash
#define NFCONF     (*(volatile unsigned *)0x4e000000)      //NAND Flash configuration
#define NFCMD      (*(volatile U8 *)0x4e000004)            //NADD Flash command
#define NFADDR     (*(volatile U8 *)0x4e000008)            //NAND Flash address
#define NFDATA     (*(volatile U8 *)0x4e00000c)            //NAND Flash data
#define NFSTAT     (*(volatile unsigned *)0x4e000010)      //NAND Flash operation status
#define NFECC      (*(volatile unsigned *)0x4e000014)      //NAND Flash ECC
#define NFECC0     (*(volatile U8  *)0x4e000014)
#define NFECC1     (*(volatile U8  *)0x4e000015)
#define NFECC2     (*(volatile U8  *)0x4e000016)

// UART
#define ULCON0     (*(volatile unsigned *)0x50000000) //UART 0 Line control
#define UCON0      (*(volatile unsigned *)0x50000004) //UART 0 Control
#define UFCON0     (*(volatile unsigned *)0x50000008) //UART 0 FIFO control
#define UMCON0     (*(volatile unsigned *)0x5000000c) //UART 0 Modem control
#define USTAT0   (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status
#define URXB0   (*(volatile unsigned *)0x50000014) //UART 0 Rx error status
#define UFSTAT0    (*(volatile unsigned *)0x50000018) //UART 0 FIFO status
#define UMSTAT0    (*(volatile unsigned *)0x5000001c) //UART 0 Modem status
#define UBRD0    (*(volatile unsigned *)0x50000028) //UART 0 Baud ate divisor

#define ULCON1     (*(volatile unsigned *)0x50004000) //UART 1 Line control
#define UCON1      (*(volatile unsigned *)0x50004004) //UART 1 Control
#define UFCON1     (*(volatile unsigned *)0x50004008) //UART 1 FIFO control
#define UMCON1     (*(volatile unsigned *)0x5000400c) //UART 1 Modem control
#define USTAT1   (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status
#define URXB1   (*(volatile unsigned *)0x50004014) //UART 1 Rx error status
#define UFSTAT1    (*(volatile unsigned *)0x50004018) //UART 1 FIFO status
#define UMSTAT1    (*(volatile unsigned *)0x5000401c) //UART 1 Modem status
#define UBRD1    (*(volatile unsigned *)0x50004028) //UART 1 Baud ate divisor

#define ULCON2     (*(volatile unsigned *)0x50008000) //UART 2 Line control
#define UCON2      (*(volatile unsigned *)0x50008004) //UART 2 Control
#define UFCON2     (*(volatile unsigned *)0x50008008) //UART 2 FIFO control
#define UMCON2     (*(volatile unsigned *)0x5000800c) //UART 2 Modem control
#define USTAT2   (*(volatile unsigned *)0x50008010) //UART 2 Tx/Rx status
#define URXB2   (*(volatile unsigned *)0x50008014) //UART 2 Rx error status
#define UFSTAT2    (*(volatile unsigned *)0x50008018) //UART 2 FIFO status
#define UMSTAT2    (*(volatile unsigned *)0x5000801c) //UART 2 Modem status
#define UBRD2    (*(volatile unsigned *)0x50008028) //UART 2 Baud ate divisor

#ifdef __BIG_ENDIAN
#define UTXH0      (*(volatile unsigned char *)0x50000023) //UART 0 Transmission Hold
#define URXH0      (*(volatile unsigned char *)0x50000027) //UART 0 Receive buffer
#define UTXH1      (*(volatile unsigned char *)0x50004023) //UART 1 Transmission Hold
#define URXH1      (*(volatile unsigned char *)0x50004027) //UART 1 Receive buffer
#define UTXH2      (*(volatile unsigned char *)0x50008023) //UART 2 Transmission Hold
#define URXH2      (*(volatile unsigned char *)0x50008027) //UART 2 Receive buffer

#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
#define RdURXH0()   (*(volatile unsigned char *)0x50000027)
#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
#define RdURXH1()   (*(volatile unsigned char *)0x50004027)
#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
#define RdURXH2()   (*(volatile unsigned char *)0x50008027)

#else //Little Endian
#define UTXH0 (*(volatile unsigned char *)0x50000020) //UART 0 Transmission Hold
#define URXH0 (*(volatile unsigned char *)0x50000024) //UART 0 Receive buffer
#define UTXH1 (*(volatile unsigned char *)0x50004020) //UART 1 Transmission Hold
#define URXH1 (*(volatile unsigned char *)0x50004024) //UART 1 Receive buffer
#define UTXH2 (*(volatile unsigned char *)0x50008020) //UART 2 Transmission Hold
#define URXH2 (*(volatile unsigned char *)0x50008024) //UART 2 Receive buffer

#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
#define RdURXH0()   (*(volatile unsigned char *)0x50000024)
#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
#define RdURXH1()   (*(volatile unsigned char *)0x50004024)
#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
#define RdURXH2()   (*(volatile unsigned char *)0x50008024)

#endif