/* * File      : start.S * This file is part of RT-Thread RTOS * COPYRIGHT (C) 2006, RT-Thread Development Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://openlab.rt-thread.com/license/LICENSE * * Change Logs: * Date           Author       Notes *                Triseel *//*! * \addtogroup AT9200 *//*@{*/#define CONFIG_STACKSIZE 4096.section .init, "ax".code 32.globl _start_start: 	ldr pc, _vector_rst	ldr	pc, _vector_undef	ldr	pc, _vector_swi	ldr	pc, _vector_pabt	ldr	pc, _vector_dabt	ldr	pc, _vector_resv	ldr	pc, _vector_irq	ldr	pc, _vector_fiq_vector_rst   : .word vector_rst_vector_undef:	.word vector_undef_vector_swi:	.word vector_swi_vector_pabt:	.word vector_pabt_vector_dabt:	.word vector_dabt_vector_resv:	.word vector_resv_vector_irq:	.word vector_irq_vector_fiq:	.word vector_fiq	.balignl 16,0xdeadbeef_TEXT_BASE:	.word	TEXT_BASE/* * rtthread kernel start and end * which are defined in linker script */.globl _rtthread_start_rtthread_start:.word _start.globl _rtthread_end_rtthread_end:	.word  _end/* * rtthread bss start and end * which are defined in linker script */.globl _bss_start_bss_start:	.word __bss_start.globl _bss_end_bss_end:	.word __bss_end/* IRQ stack memory (calculated at run-time) */IRQ_STACK_START : .word _irq_stack_start       + 1024FIQ_STACK_START : .word _fiq_stack_start       + 1024UND_STACK_START : .word _undefined_stack_start + 128ABT_STACK_START : .word _abort_stack_start     + 128SVC_STACK_START : .word _svc_stack_start       + 4096#define AT9200_BASE_AIC        	0xFFFFF000#define AT9200_AIC_IDCR_OFF    	0x124  	/*the off of disable all int reg*/#define AT9200_BASE_MC		0xFFFFFF00#define AT9200_MC_RCR_OFF	0x00	/* remap control register offset *//* the system entry */vector_rst :	/* set the cpu to SVC32 mode */	mrs	r0,cpsr	bic	r0,r0,#0x1f	orr	r0,r0,#0x13	msr	cpsr,r0	/* disable 9200 all ints */	ldr	r1, =AT9200_BASE_AIC	ldr	r0, =0xFFFFFFFF	str 	r0, [r1, #AT9200_AIC_IDCR_OFF]	/* remap memory */	ldr 	r1, =AT9200_BASE_MC	mov	r0, #0x01	str	r0, [r1, #AT9200_MC_RCR_OFF]	/* set interrupt vector */	ldr	r0, _TEXT_BASE		@source address 0x20000000, defined in config.local	mov	r1, #0x00			@target address 0x00	add	r2, r0, #0x40		@size, 16 * 4bytescopy_loop:	ldmia	r0!, {r3-r10}	@copy from source address [r0]	stmia	r1!, {r3-r10}	@copy to   target address [r1]	cmp	r0, r2				@until source end addreee [r2]	ble	copy_loop	/* setup stack */	bl	stack_setup	/* clear .bss */	mov   r0,#0                     /* get a zero 				*/	ldr   r1,=__bss_start           /* bss start 				*/	ldr   r2,=__bss_end           	/* bss end 					*/bss_loop:	cmp   r1,r2                     /* check if data to clear 	*/	strlo r0,[r1],#4                /* clear 4 bytes 			*/	blo   bss_loop                  /* loop until done 			*/	/* call C++ constructors of global objects */	ldr 	r0, =__ctors_start__	ldr 	r1, =__ctors_end__ctor_loop:	cmp 	r0, r1	beq 	ctor_end	ldr 	r2, [r0], #4	stmfd 	sp!, {r0-r1}	mov 	lr, pc	bx 		r2	ldmfd 	sp!, {r0-r1}	b 		ctor_loopctor_end:	/* start RT-Thread Kernel */	ldr	pc, _rtthread_startup_rtthread_startup: .word rtthread_startup/* ************************************************************************* * * Interrupt handling * ************************************************************************* */@@ IRQ stack frame.@#define S_FRAME_SIZE	72#define S_OLD_R0	68#define S_PSR		64#define S_PC		60#define S_LR		56#define S_SP		52#define S_IP		48#define S_FP		44#define S_R10		40#define S_R9		36#define S_R8		32#define S_R7		28#define S_R6		24#define S_R5		20#define S_R4		16#define S_R3		12#define S_R2		8#define S_R1		4#define S_R0		0#define USERMODE	0x10#define FIQMODE		0x11#define IRQMODE		0x12#define SVCMODE		0x13#define ABORTMODE	0x17#define UNDEFMODE	0x1b#define MODEMASK	0x1f#define NOINT		0xc0/* * use bad_save_user_regs for abort/prefetch/undef/swi ... */	.macro	bad_save_user_regs	sub	sp, sp, #S_FRAME_SIZE	stmia	sp, {r0 - r12}		@ Calling r0-r12	add     r8, sp, #S_PC	ldr	r2, _rtthread_end	add	r2, r2, #CONFIG_STACKSIZE	sub	r2, r2, #8	ldmia	r2, {r2 - r4}		@ get pc, cpsr, old_r0	add	r0, sp, #S_FRAME_SIZE	@ restore sp_SVC	add	r5, sp, #S_SP	mov	r1, lr	stmia	r5, {r0 - r4}		@ save sp_SVC, lr_SVC, pc, cpsr, old_r	mov	r0, sp	.endm	.macro	get_bad_stack	ldr	r13, _rtthread_end		@ setup our mode stack	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack	sub	r13, r13, #8	str	lr, [r13]				@ save caller lr / spsr	mrs	lr, spsr	str     lr, [r13, #4]	mov	r13, #SVCMODE			@ prepare SVC-Mode	msr	spsr_c, r13	mov	lr, pc	movs	pc, lr	.endm/* exception handlers */	.align  5vector_undef:	get_bad_stack	bad_save_user_regs	bl	rt_hw_trap_udef	.align	5vector_swi:	get_bad_stack	bad_save_user_regs	bl 	rt_hw_trap_swi	.align	5vector_pabt:	get_bad_stack	bad_save_user_regs	bl 	rt_hw_trap_pabt	.align	5vector_dabt:	get_bad_stack	bad_save_user_regs	bl 	rt_hw_trap_dabt	.align	5vector_resv:	get_bad_stack	bad_save_user_regs	bl 	rt_hw_trap_resv.globl rt_interrupt_enter.globl rt_interrupt_leave.globl rt_thread_switch_interrput_flag.globl rt_interrupt_from_thread.globl rt_interrupt_to_threadvector_irq:	stmfd	sp!, {r0-r12,lr}	bl	rt_interrupt_enter	bl	rt_hw_trap_irq	bl	rt_interrupt_leave	/* if rt_thread_switch_interrput_flag set, jump to _interrupt_thread_switch and don't return */	ldr	r0, =rt_thread_switch_interrput_flag	ldr	r1, [r0]	cmp	r1, #1	beq	_interrupt_thread_switch	ldmfd	sp!, {r0-r12,lr}	subs	pc, lr, #4	.align	5vector_fiq:	stmfd	sp!,{r0-r7,lr}	bl 	rt_hw_trap_fiq	ldmfd	sp!,{r0-r7,lr}	subs	pc,lr,#4_interrupt_thread_switch:	mov	r1,  #0				@ clear rt_thread_switch_interrput_flag	str	r1,  [r0]	ldmfd	sp!, {r0-r12,lr}@ reload saved registers	stmfd	sp!, {r0-r3}	@ save r0-r3	mov	r1,  sp	add	sp,  sp, #16		@ restore sp	sub	r2,  lr, #4			@ save old task's pc to r2	mrs	r3,  spsr			@ disable interrupt	orr	r0,  r3, #NOINT	msr	spsr_c, r0	ldr	r0,  =.+8			@ switch to interrupted task's stack	movs	pc,  r0	stmfd	sp!, {r2}		@ push old task's pc	stmfd	sp!, {r4-r12,lr}@ push old task's lr,r12-r4	mov	r4,  r1				@ Special optimised code below	mov	r5,  r3	ldmfd	r4!, {r0-r3}	stmfd	sp!, {r0-r3}	@ push old task's r3-r0	stmfd	sp!, {r5}		@ push old task's psr	mrs	r4,  spsr	stmfd	sp!, {r4}		@ push old task's spsr	ldr	r4,  =rt_interrupt_from_thread	ldr	r5,  [r4]	str	sp,  [r5]			@ store sp in preempted tasks's TCB	ldr	r6,  =rt_interrupt_to_thread	ldr	r6,  [r6]	ldr	sp,  [r6]			@ get new task's stack pointer	ldmfd	sp!, {r4}		@ pop new task's spsr	msr	SPSR_cxsf, r4	ldmfd	sp!, {r4}		@ pop new task's psr	msr	CPSR_cxsf, r4	ldmfd	sp!, {r0-r12,lr,pc}	@ pop new task's r0-r12,lr & pc@_interrupt_thread_switch endstack_setup:	/* undefined instruction mode */	msr cpsr_c, #UNDEFMODE|NOINT	ldr sp, UND_STACK_START	/* abort mode */	msr cpsr_c, #ABORTMODE|NOINT	ldr sp, ABT_STACK_START	/* FIQ mode */	msr cpsr_c, #FIQMODE|NOINT	ldr sp, FIQ_STACK_START	/* IRQ mode */	msr cpsr_c, #IRQMODE|NOINT	ldr sp, IRQ_STACK_START	/* supervisor mode */	msr cpsr_c, #SVCMODE|NOINT	ldr sp, SVC_STACK_START	mov	pc,lr				@ The LR register may be not valid for the mode changes.