#define AT91C_PIO_BSR		(AT91_REG(0xFFFFF474)) /* PIOA Select B Register */#define AT91C_PIO_OWER		(AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */#define AT91C_PIO_IFER		(AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */#define AT91C_PIO_PDSR		(AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */#define AT91C_PIO_PPUER		(AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */#define AT91C_PIO_OSR		(AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */#define AT91C_PIO_ASR		(AT91_REG(0xFFFFF470)) /* PIOA Select A Register */#define AT91C_PIO_MDDR		(AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */#define AT91C_PIO_CODR		(AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */#define AT91C_PIO_MDER		(AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */#define AT91C_PIO_PDR		(AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */#define AT91C_PIO_IFSR		(AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */#define AT91C_PIO_OER		(AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */#define AT91C_PIO_PSR		(AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */// ========== Register definition for PIOA peripheral ==========#define AT91C_PIOA_IMR  	(AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register#define AT91C_PIOA_IER  	(AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register#define AT91C_PIOA_OWDR 	(AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register#define AT91C_PIOA_ISR  	(AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register#define AT91C_PIOA_PPUDR 	(AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register#define AT91C_PIOA_MDSR 	(AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register#define AT91C_PIOA_MDER 	(AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register#define AT91C_PIOA_PER  	(AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register#define AT91C_PIOA_PSR  	(AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register#define AT91C_PIOA_OER  	(AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register#define AT91C_PIOA_BSR  	(AT91_REG(0xFFFFF474)) // (PIOA) Select B Register#define AT91C_PIOA_PPUER 	(AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register#define AT91C_PIOA_MDDR 	(AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register#define AT91C_PIOA_PDR  	(AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register#define AT91C_PIOA_ODR  	(AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr#define AT91C_PIOA_IFDR 	(AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register#define AT91C_PIOA_ABSR 	(AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register#define AT91C_PIOA_ASR  	(AT91_REG(0xFFFFF470)) // (PIOA) Select A Register#define AT91C_PIOA_PPUSR 	(AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register#define AT91C_PIOA_ODSR 	(AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register#define AT91C_PIOA_SODR 	(AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register#define AT91C_PIOA_IFSR 	(AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register#define AT91C_PIOA_IFER 	(AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register#define AT91C_PIOA_OSR  	(AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register#define AT91C_PIOA_IDR  	(AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register#define AT91C_PIOA_PDSR 	(AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register#define AT91C_PIOA_CODR 	(AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register#define AT91C_PIOA_OWSR 	(AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register#define AT91C_PIOA_OWER 	(AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register// ========== Register definition for PIOB peripheral ==========#define AT91C_PIOB_OWSR 	(AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register#define AT91C_PIOB_PPUSR 	(AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register#define AT91C_PIOB_PPUDR 	(AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register#define AT91C_PIOB_MDSR 	(AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register#define AT91C_PIOB_MDER 	(AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register#define AT91C_PIOB_IMR  	(AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register#define AT91C_PIOB_OSR  	(AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register#define AT91C_PIOB_OER  	(AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register#define AT91C_PIOB_PSR  	(AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register#define AT91C_PIOB_PER  	(AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register#define AT91C_PIOB_BSR  	(AT91_REG(0xFFFFF674)) // (PIOB) Select B Register#define AT91C_PIOB_PPUER 	(AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register#define AT91C_PIOB_IFDR 	(AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register#define AT91C_PIOB_ODR  	(AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr#define AT91C_PIOB_ABSR 	(AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register#define AT91C_PIOB_ASR  	(AT91_REG(0xFFFFF670)) // (PIOB) Select A Register#define AT91C_PIOB_IFER 	(AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register#define AT91C_PIOB_IFSR 	(AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register#define AT91C_PIOB_SODR 	(AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register#define AT91C_PIOB_ODSR 	(AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register#define AT91C_PIOB_CODR 	(AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register#define AT91C_PIOB_PDSR 	(AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register#define AT91C_PIOB_OWER 	(AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register#define AT91C_PIOB_IER  	(AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register#define AT91C_PIOB_OWDR 	(AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register#define AT91C_PIOB_MDDR 	(AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register#define AT91C_PIOB_ISR  	(AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register#define AT91C_PIOB_IDR  	(AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register#define AT91C_PIOB_PDR  	(AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register/* ========== Register definition for PMC peripheral ========== */#define AT91C_PMC_SCER		(AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */#define AT91C_PMC_SCDR		(AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */#define AT91C_PMC_SCSR		(AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */#define AT91C_PMC_PCER		(AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */#define AT91C_PMC_PCDR		(AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */#define AT91C_PMC_PCSR		(AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */#define AT91C_PMC_MOR		(AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */#define AT91C_PMC_MCFR		(AT91_REG(0xFFFFFC24)) /* PMC Main Clock  Frequency Register */#define AT91C_PMC_PLLR		(AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */#define AT91C_PMC_MCKR		(AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */#define AT91C_PMC_PCKR		(AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */#define AT91C_PMC_IER		(AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */#define AT91C_PMC_IDR		(AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */#define AT91C_PMC_SR		(AT91_REG(0xFFFFFC68)) /* PMC Status Register */#define AT91C_PMC_IMR		(AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register *//******************************************************************************/
/*               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64                    */
/******************************************************************************/
#define AT91C_ID_FIQ    	0 	/* Advanced Interrupt Controller (FIQ) */
#define AT91C_ID_SYS    	1 	/* System Peripheral */
#define AT91C_ID_PIOA   	2 	/* Parallel IO Controller A */
#define AT91C_ID_PIOB   	3 	/* Parallel IO Controller B */#define AT91C_ID_ADC    	4 	/* Analog-to-Digital Converter */
#define AT91C_ID_SPI    	5	/* Serial Peripheral Interface */
#define AT91C_ID_US0    	6	/* USART 0 */
#define AT91C_ID_US1    	7	/* USART 1 */
#define AT91C_ID_SSC    	8	/* Serial Synchronous Controller */
#define AT91C_ID_TWI    	9 	/* Two-Wire Interface */
#define AT91C_ID_PWMC   	10	/* PWM Controller */
#define AT91C_ID_UDP    	11 	/* USB Device Port */
#define AT91C_ID_TC0    	12 	/* Timer Counter 0 */
#define AT91C_ID_TC1    	13 	/* Timer Counter 1 */
#define AT91C_ID_TC2    	14 	/* Timer Counter 2 */
#define AT91C_ID_15			15	/* Reserved */
#define AT91C_ID_16 		16 	/* Reserved */
#define AT91C_ID_17 		17 	/* Reserved */
#define AT91C_ID_18 		18 	/* Reserved */
#define AT91C_ID_19 		19 	/* Reserved */
#define AT91C_ID_20 		20 	/* Reserved */
#define AT91C_ID_21 		21 	/* Reserved */
#define AT91C_ID_22 		22 	/* Reserved */
#define AT91C_ID_23 		23 	/* Reserved */
#define AT91C_ID_24 		24 	/* Reserved */
#define AT91C_ID_25 		25 	/* Reserved */
#define AT91C_ID_26 		26 	/* Reserved */
#define AT91C_ID_27 		27 	/* Reserved */
#define AT91C_ID_28 		28 	/* Reserved */
#define AT91C_ID_29 		29 	/* Reserved */
#define AT91C_ID_IRQ0		30 	/* Advanced Interrupt Controller (IRQ0) */
#define AT91C_ID_IRQ1		31 	/* Advanced Interrupt Controller (IRQ1) */
#define AT91C_ALL_INT		0xC0007FF7	/* ALL VALID INTERRUPTS */
#define MCK	48054857/*****************************//* CPU Mode                  *//*****************************/#define USERMODE			0x10#define FIQMODE				0x11#define IRQMODE				0x12#define SVCMODE				0x13#define ABORTMODE			0x17#define UNDEFMODE			0x1b#define MODEMASK			0x1f#define NOINT				0xc0#ifdef __cplusplus}#endif#endif