?? des_ctrl.v
字號:
/*-----------------------------------------------------------------------
/Module : DES_CTRL
/Filename : DES_CTRL.v
/Description : DES
/Called by : DES
/Simulator : Modelsim5.7 and Simvision / WindowsXP
/Synthesis tool : Synplify / WindowsXP
/Revision history : 2008-05-30 v1.0
--------------------------------------------------------------------------*/
module DES_CTRL(
clk,
rst_n,
sw_rst,
key_321,
work_mode,
s_width,
DES_encrypt_start,
DES_decrypt_start,
//DES3_encrypt_start,
//DES3_decrypt_start,
load_data,
load_key,
load_iv,
//buff_out_load,
//Left_first,
ready,
lut_en,
ls1,ls2,ls3,ls4,ls5,ls6,ls7,ls8,ls9,ls10,ls11,ls12,ls13,ls14,ls15,ls16,
dls2,dls3,dls4,dls5,dls6,dls7,dls8,dls9,dls10,dls11,dls12,dls13,dls14,dls15,dls16,
IP,
data_sel_iv,
data_sel_buff,
data_sel_com1,
data_sel_com2,
k1_sel_key1,
k2_sel_key2,
k3_sel_key3,
key_sel_k1,
key_sel_k2,
key_sel_k3,
iv_sel_tmp,
iv_sel_data,
//tmp_sel_data,
tmp_sel_buff,
IP_1,
buff_xor_iv,
data_xor_iv,
tmp_xor_data_1,
tmp_xor_data_8,
tmp_xor_data_16,
tmp_xor_data_32,
tmp_xor_data_64,
iv_shift_1,
iv_shift_8,
iv_shift_16,
iv_shift_32,
iv_shift_64,
iv_back_tmp,
buff_load,
buff_load_low,
iv_load
//sel_left,
//sel_right
);
input clk; //systerm clk
input rst_n; //reset signal
input sw_rst; //soft reset signal
input [2:0] key_321; //how many keys
input [4:0] s_width; //the width of s bit
//input buff_out_load;
//input Left_first;
input load_data; //load data enable signal
input load_key; //load key enable signal
input load_iv; //load iv enable signal
input [4:0] work_mode; //work mode of des
input DES_encrypt_start; //des encipher plaintext start signal
input DES_decrypt_start; //des decipher cipertext start signal
//input DES3_encrypt_start; //3des encipher plaintext start signal
//input DES3_decrypt_start; //3des decipher cipertext start signal
output ready; //des finish signal
output lut_en; //f_fuction enable signal;
output ls1,ls2,ls3,ls4,ls5,ls6,ls7,ls8,ls9,ls10,ls11,ls12,ls13,ls14,ls15,ls16;
//key left shift enable signal
output dls2,dls3,dls4,dls5,dls6,dls7,dls8,dls9,dls10,dls11,dls12,dls13,dls14,dls15,dls16;
//key right shift enable signal
output IP; //IP change enable signal
output data_sel_iv; //data_reg select iv_reg
output data_sel_buff; //buff_reg to data_reg
output data_sel_com1; //data_reg select {data_reg[32:63],r2}
output data_sel_com2; //data_reg select {r2,data_reg[32:63]}
output k1_sel_key1; //k1 select buffin
output k2_sel_key2; //k2_select buffin
output k3_sel_key3; //k3_select buffin
output key_sel_k1; //x2 port select k1_reg
output key_sel_k2; //x2 port select k2_reg
output key_sel_k3; //x2 port select k3_reg
output iv_sel_tmp; //tmp to iv resigster
output iv_sel_data; //data_reg to iv resigster
output tmp_sel_buff; //buff_reg to tmp reg
output IP_1; //IP-1 change;
output buff_xor_iv; //buff exclusive-or iv
output data_xor_iv; //data exclusive-or iv
output tmp_xor_data_1; //tmp exclusive-or data 1bit
output tmp_xor_data_8; //tmp exclusive-or data 8bits
output tmp_xor_data_16; //tmp exclusive-or data 16bits
output tmp_xor_data_32; //tmp exclusive-or data 32bits
output tmp_xor_data_64; //tmp exclusive-or data 64bits
output iv_shift_1; //iv left shift 1bit
output iv_shift_8; //iv left shift 8bits
output iv_shift_16; //iv left shift 16bits
output iv_shift_32; //iv left shift 32bits;
output iv_shift_64; //iv left shift 64bits;
output iv_back_tmp; //iv back tmp_reg
output buff_load; //buffin to buff
output buff_load_low; //only load 32bit(most) to buff_reg
output iv_load; //buffin to iv
//output sel_left;
//output sel_right;
wire s_1,s_8,s_16,s_32,s_64;
wire ECB,CBC,OFB,CFB;
reg des_encrypt_busy,des_decrypt_busy,des3_encrypt_busy,des3_decrypt_busy;
reg des_busy,des3_busy;
/***********************work mode des and 3des fsm signal****************/
reg [3:0] des_mode_current_state;
reg [3:0] des_mode_next_state;
parameter des_mode_idle_state =4'b0000; //work mode des or 3des idle state;
parameter des_mode_buff_2_data_1_state =4'b0001; //work mode des or 3des buff_reg to data_reg
parameter des_mode_des_cal_1_state =4'b0010; //work mode des calculate
parameter des_mode_des3_cal_1_state =4'b0011; //work mode 3des calculate
parameter des_mode_buff_xor_iv_state =4'b0100; //buff_reg or iv_reg
parameter des_mode_buff_2_data_2_state =4'b0101; //buff_reg to data_reg
parameter des_mode_des_cal_2_state =4'b0110; //des calculate
parameter des_mode_des3_cal_2_state =4'b0111; //3des calculate
parameter des_mode_data_2_iv_state =4'b1000; //data_reg to iv_reg
parameter des_mode_data_xor_iv_state =4'b1001; //data_reg xor iv_reg
parameter des_mode_iv_2_data_state =4'b1010; //iv_reg to data_reg
parameter des_mode_des_cal_3_state =4'b1011; //des calculate
parameter des_mode_des3_cal_3_state =4'b1100; //3des calculate
parameter des_mode_tmp_xor_data_state =4'b1101; //tmp_reg xor data_reg
parameter des_mode_iv_back_shift_state =4'b1110; //iv shift
parameter des_mode_finish_state =4'b1111; //des or 3des finish state
wire buff_2_data,buff_xor_iv,data_2_iv,data_xor_iv,iv_2_data,tmp_xor_data,iv_shift;
/************************************************************************/
/******************************3des fsm signal***************************/
reg [1:0] des3_current_state;
reg [1:0] des3_next_state;
parameter des3_idle_state =2'b00; //3des idle state;
parameter des3_des1_state =2'b01; //3des the first des operation
parameter des3_des2_state =2'b10; //3des the second des opteration
parameter des3_des3_state =2'b11; //3des the thibuff_out_load des opteration
//parameter des3_ready_state =3'b100; //3des finish state
wire des3_ready,des_encrypt,des_decrypt,des_start,des3_start;
wire des1_state,des2_state,des3_state;
wire key_sel_k1,key_sel_k2,key_sel_k3;
/************************************************************************/
/******************************des_fsm signal****************************/
reg [4:0] des_current_state;
reg [4:0] des_next_state;
parameter des_idle_state =5'b00000; //des idle state
parameter des_IP_state =5'b00001; //des ip change state
parameter des_lut1_state =5'b00010; //des round 1 state
parameter des_lut2_state =5'b00011; //des round 2 state
parameter des_lut3_state =5'b00100; //des round 3 state
parameter des_lut4_state =5'b00101; //des round 4 state
parameter des_lut5_state =5'b00110; //des round 5 state
parameter des_lut6_state =5'b00111; //des round 6 state
parameter des_lut7_state =5'b01000; //des round 7 state
parameter des_lut8_state =5'b01001; //des round 8 state
parameter des_lut9_state =5'b01010; //des round 9 state
parameter des_lut10_state =5'b01011; //des round 10 state
parameter des_lut11_state =5'b01100; //des round 11 state
parameter des_lut12_state =5'b01101; //des round 12 state
parameter des_lut13_state =5'b01110; //des round 13 state
parameter des_lut14_state =5'b01111; //des round 14 state
parameter des_lut15_state =5'b10000; //des round 15 state
parameter des_lut16_state =5'b10001; //des round 16 state
parameter des_IP_1_state =5'b10010; //des ip-1 change state
parameter des_ready_state =5'b10011; //des ready state
wire IP,lut_en,IP_1,des_ready;
wire ls1,ls2,ls3,ls4,ls5,ls6,ls7,ls8,ls9,ls10,ls11,ls12,ls13,ls14,ls15,ls16;
wire dls2,dls3,dls4,dls5,dls6,dls7,dls8,dls9,dls10,dls11,dls12,dls13,dls14,dls15,dls16;
wire IP_state,lut1_state,lut2_state,lut3_state,lut4_state,lut5_state,lut6_state,lut7_state;
wire lut8_state,lut9_state,lut10_state,lut11_state,lut12_state,lut13_state,lut14_state,lut15_state,lut16_state,IP_1_state;
/*************************work mode signal*******************************/
assign ECB=work_mode[0];
assign CBC=work_mode[1];
assign CFB=work_mode[2];
assign OFB=work_mode[3];
//assign ECB=(work_mode[1:0]==2'b00)?1'b1:1'b0;
//assign CBC=(work_mode[1:0]==2'b01)?1'b1:1'b0;
//assign CFB=(work_mode[1:0]==2'b10)?1'b1:1'b0;
//assign OFB=(work_mode[1:0]==2'b11)?1'b1:1'b0;
/************************************************************************/
/************************the number of key******************************/
wire key_1,key_2,key_3;
assign key_1=key_321[0];
assign key_2=key_321[1];
assign key_3=key_321[2];
/***********************************************************************/
wire DES3_encrypt_start;
wire DES3_decrypt_start;
assign DES3_encrypt_start=DES_encrypt_start && (key_2|key_3);
assign DES3_decrypt_start=DES_decrypt_start && (key_2|key_3);
/*************************the wide of s*********************************/
assign s_1=s_width[0];
assign s_8=s_width[1];
assign s_16=s_width[2];
assign s_32=s_width[3];
assign s_64=s_width[4];
/***********************************************************************/
reg [2:0] counter;
//------------------------------------------------------------------
//k1_reg select buffin enable signal
//------------------------------------------------------------------
assign k1_sel_key1=(counter[2:1]==2'b00 &&load_key)?1'b1:1'b0;
assign k2_sel_key2=(counter[2:1]==2'b01 && (key_2||key_3) && load_key)?1'b1:1'b0;
assign k3_sel_key3=(((counter[2:1]==2'b10 && key_3)||(counter[2:1]==2'b00 && key_2)) && load_key)?1'b1:1'b0;
//------------------------------------------------------------------
//buff_reg load data enable signal
//------------------------------------------------------------------
assign buff_load=load_data;
assign buff_load_low=(buff_load && (CFB||OFB) && (s_1||s_8||s_16||s_32))? 1'b1:1'b0;
//------------------------------------------------------------------
//buff_reg load iv enable signal
//------------------------------------------------------------------
assign iv_load=load_iv;
//----------------------------
//how the counter work
//----------------------------
wire counter_inc,counter_clr;
assign counter_inc=load_key || load_data;
assign counter_clr=((load_key && ((key_3 && counter==3'b101)||(key_2 && counter==3'b011)||(key_1 && counter==3'b001)))||
(load_data &&((counter==3'b001)||
(counter==3'b000&&(s_1||s_8||s_16||s_32)&&(CFB || OFB))
)))?1'b1:1'b0;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) counter<=3'b000;
else if(sw_rst) counter<=3'b000;
else
begin
if(counter_clr) counter<=3'b000;
else if(counter_inc) counter<=counter+1'b1;
end
end
/************************busy_signal*************************************/
//----------------------------
//DES encipher busy signal
//---------------------------
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
des_encrypt_busy<=1'b0;
else
if(sw_rst) des_encrypt_busy<=1'b0;
else
begin
if(ready) des_encrypt_busy<=1'b0;
else if((DES_encrypt_start&&(!DES3_encrypt_start)) || (DES_decrypt_start&&(!DES3_decrypt_start)&& (CFB||OFB))) des_encrypt_busy<=1'b1;
end
end
//----------------------------
//DES decipher busy signal
//---------------------------
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
des_decrypt_busy<=1'b0;
else
if(sw_rst) des_decrypt_busy<=1'b0;
else
begin
if(ready) des_decrypt_busy<=1'b0;
else if((DES_decrypt_start&&(!DES3_decrypt_start)) &&(ECB || CBC)) des_decrypt_busy<=1'b1;
end
end
//---------------------------
//3DES encipher busy signal
//--------------------------
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
des3_encrypt_busy<=1'b0;
else
if(sw_rst) des3_encrypt_busy<=1'b0;
else
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