module wallace(a,b,prod);
input [5:0] a,b;
output [11:0] prod;

wire [11:0] pp0,pp1,pp2,pp4,pp3,pp5;
wire [11:0] c0,s0,c1,s1,s2,c2,s3,c3;
wire c00,s00,c01,s01,c02,s02,c03,s03,c04,s04,c05,s05,c06,s06,c07,s07;
wire c10,s10,c11,s11,c12,s12,c13,s13,c14,s14,c15,s15,c16,s16,c17,s17,c18,s18,c19,s19,c119,s119,c118,s118;
wire c20,s20,c21,s21,c22,s22,c23,s23,c24,s24,c25,s25,c26,s26,c27,s27,c28,s28,c29,s29,c210,s210;
wire c30,s30,c31,s31,c32,s32,c33,s33,c34,s34,c35,s35,c36,s36,c37,s37,c38,s38,c39,s39,c310,s310,c311,s311;

assign pp0={6'b0,a&{6{b[0]}}};
assign pp1={5'b0,a&{6{b[1]}},1'b0};
assign pp2={4'b0,a&{6{b[2]}},2'b0};
assign pp3={3'b0,a&{6{b[3]}},3'b0};
assign pp4={2'b0,a&{6{b[4]}},4'b0};
assign pp5={1'b0,a&{6{b[5]}},5'b0};

assign {c00,s00}=pp0[0]+pp1[0]+pp2[0];
assign {c01,s01}=pp0[1]+pp1[1]+pp2[1];
assign {c02,s02}=pp0[2]+pp1[2]+pp2[2];
assign {c03,s03}=pp0[3]+pp1[3]+pp2[3];
assign {c04,s04}=pp0[4]+pp1[4]+pp2[4];
assign {c05,s05}=pp0[5]+pp1[5]+pp2[5];
assign {c06,s06}=pp0[6]+pp1[6]+pp2[6];
assign {c07,s07}=pp0[7]+pp1[7]+pp2[7];
//
===============================assign {c18,s18}=pp3[0]+pp4[0]+pp5[0];
assign {c19,s19}=pp3[1]+pp4[1]+pp5[1];

assign {c118,s118}=pp3[2]+pp4[2]+pp5[2];
assign {c119,s119}=pp3[3]+pp4[3]+pp5[3];
assign {c10,s10}=pp3[4]+pp4[4]+pp5[4];
assign {c11,s11}=pp3[5]+pp4[5]+pp5[5];
assign {c12,s12}=pp3[6]+pp4[6]+pp5[6];
assign {c13,s13}=pp3[7]+pp4[7]+pp5[7];
assign {c14,s14}=pp3[8]+pp4[8]+pp5[8];
assign {c15,s15}=pp3[9]+pp4[9]+pp5[9];
assign {c16,s16}=pp3[10]+pp4[10]+pp5[10];
assign {c17,s17}=pp3[11]+pp4[11]+pp5[11];

assign c0={3'b0,c07,c06,c05,c04,c03,c02,c01,c00,1'b0};
assign s0={4'b0,s07,s06,s05,s04,s03,s02,s01,s00};
assign c1={c16,c15,c14,c13,c12,c11,c10,c119,c118,c19,c18,1'b0};
assign s1={s17,s16,s15,s14,s13,s12,s11,s10,s119,s118,s19,s18};

assign {c20,s20}=c0[0]+s0[0]+s1[0];
assign {c21,s21}=c0[1]+s0[1]+s1[1];
assign {c22,s22}=c0[2]+s0[2]+s1[2];
assign {c23,s23}=c0[3]+s0[3]+s1[3];
assign {c24,s24}=c0[4]+s0[4]+s1[4];
assign {c25,s25}=c0[5]+s0[5]+s1[5];
assign {c26,s26}=c0[6]+s0[6]+s1[6];
assign {c27,s27}=c0[7]+s0[7]+s1[7];
assign {c28,s28}=c0[8]+s0[8]+s1[8];
assign {c29,s29}=c0[9]+s0[9]+s1[9];
assign {c210,s210}=c0[10]+s0[10]+s1[10];
assign c2={c210,c29,c28,c27,c26,c25,c24,c23,c22,c21,c20,1'b0};
assign s2={1'b0,s210,s29,s28,s27,s26,s25,s24,s23,s22,s21,s20};

assign {c30,s30}=c2[0]+s2[0]+c1[0];
assign {c31,s31}=c2[1]+s2[1]+c1[1];
assign {c32,s32}=c2[2]+s2[2]+c1[2];
assign {c33,s33}=c2[3]+s2[3]+c1[3];
assign {c34,s34}=c2[4]+s2[4]+c1[4];
assign {c35,s35}=c2[5]+s2[5]+c1[5];
assign {c36,s36}=c2[6]+s2[6]+c1[6];
assign {c37,s37}=c2[7]+s2[7]+c1[7];
assign {c38,s38}=c2[8]+s2[8]+c1[8];
assign {c39,s39}=c2[9]+s2[9]+c1[9];
assign {c310,s310}=c2[10]+s2[10]+c1[10];
assign {c311,s311}=c2[11]+s2[11]+c1[11];


assign c3={c310,c39,c38,c37,c36,c35,c34,c33,c32,c31,c30,1'b0};
assign s3={s311,s310,s39,s38,s37,s36,s35,s34,s33,s32,s31,s30};

assign prod[0]=s3[0]+c3[0];
assign prod[1]=s3[1]+c3[1];
assign prod[2]=s3[2]+c3[2];
assign prod[3]=s3[3]+c3[3];
assign prod[4]=s3[4]+c3[4];
assign prod[5]=s3[5]+c3[5];
assign prod[6]=s3[6]+c3[6];
assign prod[7]=s3[7]+c3[7];
assign prod[8]=s3[8]+c3[8];
assign prod[9]=s3[9]+c3[9];
assign prod[10]=s3[10]+c3[10];
assign prod[11]=s3[11]+c3[11];


endmodule