library IEEE;use  IEEE.std_logic_1164.all;use  IEEE.std_logic_ARITH.all;use  IEEE.std_logic_UNSIGNED.all;	ENTITY Test_CY7C1062AV33 IS	PORT	(			-- Entr閑s		CLOCK						: in 	std_logic;  			RESET_n    				: in 	std_logic;					CDE_ECRITURE			: in 	std_logic;		CDE_LECTURE				: in 	std_logic;		DATA_TEST_i 			: in std_logic_vector (31 downto 0); 		-- Sorties		FPGA_PPC_LALE			: out std_logic;		FPGA_PPC_SRAM_BAn		: out std_logic;		FPGA_PPC_SRAM_BBn		: out std_logic;		FPGA_PPC_SRAM_BCn		: out std_logic;		FPGA_PPC_SRAM_BDn		: out std_logic;		FPGA_PPC_SRAM_OEn		: out std_logic;		FPGA_PPC_SRAM_WEn		: out std_logic;		FPGA_PPC_SRAM_CE1n	: out std_logic;		DATA_TEST_o 			: out std_logic_vector (31 downto 0); 		-- Entr閑s/Sortie		FPGA_PPC_IO				: inout std_logic_vector (31 downto 0)	);	END Test_CY7C1062AV33;ARCHITECTURE Test_CY7C1062AV33 OF Test_CY7C1062AV33 ISsignal State : std_logic_vector(4 downto 0);signal cnt : std_logic;begin	process (CLOCK ,RESET_n)	begin		if (RESET_n = '0') then						FPGA_PPC_SRAM_BAn		<= '1';			FPGA_PPC_SRAM_BBn		<= '1';			FPGA_PPC_SRAM_BCn		<= '1';			FPGA_PPC_SRAM_BDn		<= '1';			FPGA_PPC_SRAM_OEn		<= '1';			FPGA_PPC_SRAM_WEn		<= '1';			FPGA_PPC_SRAM_CE1n	<= '1';			FPGA_PPC_LALE			<= '1';			FPGA_PPC_IO				<= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";						state	<= "00100";			cnt <= '0';				elsif ( rising_edge(CLOCK) ) then					case State is								when "00100" =>					cnt <= '0';					if( CDE_ECRITURE = '1' ) then						FPGA_PPC_LALE			<= '1';						FPGA_PPC_IO				<= DATA_TEST_i;						state						<= "01000";					elsif ( CDE_LECTURE = '1' ) then						FPGA_PPC_LALE			<= '1';						FPGA_PPC_IO				<= DATA_TEST_i;						state						<= "00010";										else						FPGA_PPC_SRAM_BAn		<= '1';						FPGA_PPC_SRAM_BBn		<= '1';						FPGA_PPC_SRAM_BCn		<= '1';						FPGA_PPC_SRAM_BDn		<= '1';						FPGA_PPC_SRAM_OEn		<= '1';						FPGA_PPC_SRAM_WEn		<= '1';						FPGA_PPC_SRAM_CE1n	<= '1';						FPGA_PPC_LALE			<= '0';						FPGA_PPC_IO				<= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";											end if;									when "01000" =>						FPGA_PPC_SRAM_BAn		<= '0';						FPGA_PPC_SRAM_BBn		<= '0';						FPGA_PPC_SRAM_BCn		<= '0';						FPGA_PPC_SRAM_BDn		<= '0';						FPGA_PPC_SRAM_OEn		<= '0';						FPGA_PPC_SRAM_WEn		<= '0';						FPGA_PPC_SRAM_CE1n	<= '0';						FPGA_PPC_LALE			<= '0';						FPGA_PPC_IO				<= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";						state						<= "10000";				when "10000" =>					FPGA_PPC_IO	<= not DATA_TEST_i;					if (cnt = '1') then						FPGA_PPC_SRAM_BAn		<= '1';						FPGA_PPC_SRAM_BBn		<= '1';						FPGA_PPC_SRAM_BCn		<= '1';						FPGA_PPC_SRAM_BDn		<= '1';						FPGA_PPC_SRAM_OEn		<= '1';						FPGA_PPC_SRAM_WEn		<= '1';						FPGA_PPC_SRAM_CE1n	<= '1';						FPGA_PPC_LALE			<= '0';						state						<= "00100";					end if;					cnt <= '1';									when "00010" =>					FPGA_PPC_LALE			<= '0';					FPGA_PPC_IO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";					if (cnt = '1') then						FPGA_PPC_SRAM_BAn		<= '0';						FPGA_PPC_SRAM_BBn		<= '0';						FPGA_PPC_SRAM_BCn		<= '0';						FPGA_PPC_SRAM_BDn		<= '0';						FPGA_PPC_SRAM_OEn		<= '0';						FPGA_PPC_SRAM_CE1n	<= '0';						state						<= "00001";					end if;					cnt <= '1';									when "00001" =>					FPGA_PPC_SRAM_BAn		<= '1';					FPGA_PPC_SRAM_BBn		<= '1';					FPGA_PPC_SRAM_BCn		<= '1';					FPGA_PPC_SRAM_BDn		<= '1';					FPGA_PPC_SRAM_OEn		<= '0';					FPGA_PPC_SRAM_CE1n	<= '0';					data_test_o				<= FPGA_PPC_IO;					state						<= "00100";							when others =>					state	<= "00100";												end case;						end if;		end process;END Test_CY7C1062AV33;