library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity PS2 is
    port ( KBdata: in STD_LOGIC;
           KBCLK:  in STD_LOGIC;
           DOUT:   out STD_LOGIC_VECTOR(7 downto 0);
--           CLKIN:  in STD_LOGIC;
           NUM:    out std_logic_vector(6 downto 0);
           rst:    in std_logic );
end PS2;

architecture PS2_arch of PS2 is

signal test: std_logic;
signal CLK: std_logic;
signal M, S: std_logic_vector(9 downto 0);
signal N2: std_logic_vector(4 downto 0);
signal DREG: std_logic_vector(7 downto 0);
signal N: std_logic_vector(5 downto 0);
begin
--process(CLKIN)
--begin
--if (KBCLK='1') then
--	CLK<= '1';
--elsif (CLKIN'event and CLKIN='1') then
--	CLK <= KBCLK;
--end if;
--end process;	
CLK<=KBCLK;
process(CLK, KBDATA, S)
begin
--if RST='0' or N=33 then
--		N<=(others=>'0');
if (CLK'event and CLK='0') then
--	N<=N+1;
--	if N<12 then
		S <= KBDATA & S(9 DOWNTO 1);
	end if;
--end process;

--process(clk, M, N2, KBdata)
--begin
--if (CLK'EVENT AND CLK='1') THEN
--   S <= M;
--end if;
	DOUT <= not(S(7 downto 0));
	case S(7 downto 0) is
		when 	"00010110" => NUM <= "1111001";
	  	when 	"00011110" => NUM <= "0100100";
	  	when 	"00100110" => NUM <= "0110000";
	  	when 	"00100101" => NUM <= "0011001";
	  	when 	"00101110" => NUM <= "0010010";
	  	when 	"00110110" => NUM <= "0000010";
	  	when 	"00111101" => NUM <= "1111000";
		when 	"00111110" => NUM <= "0000000";
		when 	"01000110" => NUM <= "0010000";
	  	when 	"01000101" => NUM <= "1000000";
		when  "00011100" => NUM <= "0001000";
		when  "00110010" => NUM <= "0000011";
		when  "00100001" => NUM <= "1000110";
		when  "00100011" => NUM <= "0100001";
		when  "00100100" => NUM <= "0000110";
		when  "00101011" => NUM <= "0001110";
		when 	others     => NUM <= "0000000";
	end case;
--	end if;
end process;

test <= not(CLK);

end PS2_arch;