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-- You must compile the wrapper file fft_2s.vhd when simulating
-- the core, fft_2s. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY fft_2s IS
	port (
	clk: IN std_logic;
	ce: IN std_logic;
	reset: IN std_logic;
	start: IN std_logic;
	fwd_inv: IN std_logic;
	mrd: IN std_logic;
	mwr: IN std_logic;
	xn_re: IN std_logic_VECTOR(7 downto 0);
	xn_im: IN std_logic_VECTOR(7 downto 0);
	ovflo: OUT std_logic;
	done: OUT std_logic;
	edone: OUT std_logic;
	busy: OUT std_logic;
	xk_re: OUT std_logic_VECTOR(7 downto 0);
	xk_im: OUT std_logic_VECTOR(7 downto 0));
END fft_2s;

ARCHITECTURE fft_2s_a OF fft_2s IS
-- synopsys translate_off
component wrapped_fft_2s
	port (
	clk: IN std_logic;
	ce: IN std_logic;
	reset: IN std_logic;
	start: IN std_logic;
	fwd_inv: IN std_logic;
	mrd: IN std_logic;
	mwr: IN std_logic;
	xn_re: IN std_logic_VECTOR(7 downto 0);
	xn_im: IN std_logic_VECTOR(7 downto 0);
	ovflo: OUT std_logic;
	done: OUT std_logic;
	edone: OUT std_logic;
	busy: OUT std_logic;
	xk_re: OUT std_logic_VECTOR(7 downto 0);
	xk_im: OUT std_logic_VECTOR(7 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_fft_2s use entity XilinxCoreLib.vfft32_v3_0(behavioral)
		generic map(
			butterfly_precision => 8,
			c_family_int => 0,
			data_memory => "block_mem",
			phase_factor_precision => 8,
			memory_architecture => 3,
			mult_type => 0,
			scaling_schedule_mem2 => "fft_2s_mem2.mif",
			scaling_schedule_mem1 => "fft_2s_mem1.mif");
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_fft_2s
		port map (
			clk => clk,
			ce => ce,
			reset => reset,
			start => start,
			fwd_inv => fwd_inv,
			mrd => mrd,
			mwr => mwr,
			xn_re => xn_re,
			xn_im => xn_im,
			ovflo => ovflo,
			done => done,
			edone => edone,
			busy => busy,
			xk_re => xk_re,
			xk_im => xk_im);
-- synopsys translate_on

END fft_2s_a;