# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = F:\Xilinx\OpenHard\HDL_file\counter_coreSET speedgrade = -7SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc2s200eSET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = pq208SET createndf = FalseSET designentry = VHDLSET devicefamily = spartan2eSET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Binary_Counter family Xilinx,_Inc. 6.0# END Select# BEGIN ParametersCSET count_style=count_by_constantCSET create_rpm=trueCSET output_width=8CSET async_init_value=0CSET threshold_0=falseCSET threshold_1=falseCSET synchronous_settings=noneCSET count_to_value=MAXCSET threshold_1_value=MAXCSET clock_enable=trueCSET threshold_0_value=MAXCSET asynchronous_settings=clearCSET ce_overrides=sync_controls_override_ceCSET load=trueCSET set_clear_priority=clear_overrides_setCSET component_name=counterCSET count_by_value=1CSET threshold_early=trueCSET restrict_count=falseCSET operation=up_downCSET sync_init_value=0CSET ce_override_for_load=falseCSET threshold_options=non_registeredCSET load_sense=active_high# END ParametersGENERATE