-- VHDL Test Bench Created from source file radarsima.vhd -- 15:51:42 11/05/2003
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT radarsima
	PORT(
		trig_key_in : IN std_logic;
		azip_key_in : IN std_logic;
		rst_in : IN std_logic;
		clk_in : IN std_logic;          
		trig_out : OUT std_logic;
		azip_out : OUT std_logic;
		shf_out : OUT std_logic;
		video_out : OUT std_logic;
		azip_led_common : buffer std_logic_vector(3 downto 0);
		trig_led_common : buffer std_logic_vector(3 downto 0);
		trig_led : OUT std_logic_vector(6 downto 0);
		azip_led : OUT std_logic_vector(6 downto 0);
		trigkey_test : OUT std_logic;
		temp : OUT std_logic
		);
	END COMPONENT;

	SIGNAL trig_out :  std_logic;
	SIGNAL trig_key_in :  std_logic	:=	'0';
	SIGNAL azip_out :  std_logic;
	SIGNAL azip_key_in :  std_logic	:= '0';
	SIGNAL shf_out :  std_logic;
	SIGNAL video_out :  std_logic;
	SIGNAL rst_in :  std_logic	:=	'1';
	SIGNAL clk_in :  std_logic	:= '1';
	SIGNAL azip_led_common :  std_logic_vector(3 downto 0);
	SIGNAL trig_led_common :  std_logic_vector(3 downto 0);
	SIGNAL trig_led :  std_logic_vector(6 downto 0);
	SIGNAL azip_led :  std_logic_vector(6 downto 0);
	SIGNAL trigkey_test :  std_logic;
	SIGNAL temp :  std_logic;

BEGIN

	uut: radarsima PORT MAP(
		trig_out => trig_out,
		trig_key_in => trig_key_in,
		azip_out => azip_out,
		azip_key_in => azip_key_in,
		shf_out => shf_out,
		video_out => video_out,
		rst_in => rst_in,
		clk_in => clk_in,
		azip_led_common => azip_led_common,
		trig_led_common => trig_led_common,
		trig_led => trig_led,
		azip_led => azip_led,
		trigkey_test => trigkey_test,
		temp => temp
	);

	process
	begin
		wait for 12.9 ns;
		clk_in	<=	not clk_in;
	end process;

	rst_in	<=	'0'	after 73.7 ns;

END;